SEMICONDUCTOR DEVICE

• US 20080308848A1
• Filed: 05/12/2008
• Published: 12/18/2008
• Est. Priority Date: 05/15/2007
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: INABA, Satoshi
• Granted Patent: US 7,994,583 B2
• Time in Patent Office: Days
• US Class Current: 257/255
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A semiconductor device according to an aspect of the invention comprises an n-type FinFET which is provided on a semiconductor substrate and which includes a first fin, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions provided at both end of the first fin, a p-type FinFET which is provided on the semiconductor substrate and which includes a second fin, a second gate electrode crossing a channel region of the second fin via a gate insulating film in three dimensions, and contact regions provided at both end of the second fin, wherein the n- and the p-type FinFET constitute an inverter circuit, and the fin width of the contact region of the p-type FinFET is greater than the fin width of the channel region of the n-type FinFET.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

an n-type FinFET which is provided on the semiconductor substrate and which includes a first fin acting as an active region, a first gate electrode crossing a channel region of the first fin via a gate insulating film in three dimensions, and contact regions provided at one end and the other end of the first fin and sandwiching the channel region;

a p-type FinFET which is provided on the semiconductor substrate and which includes a second fin acting as an active region, a second gate electrode crossing a channel region of the second fin via a gate insulating film in three dimensions, and contact regions provided at one end and the other end of the second fin and sandwiching the channel region,

wherein the n-type FinFET and the p-type FinFET constitute an inverter circuit, and

the fin width of the contact region of the p-type FinFET to act as an output node of the inverter circuit is greater than the fin width of the channel region of the n-type FinFET.

2. The semiconductor device according to claim 1, wherein the fin width of the channel region of the p-type FinFET is greater than the width of the channel region of the n-type FinFET.

3. The semiconductor device according to claim 1, wherein the fin width of the contact region of the p-type FinFET is greater than the fin width of the channel region of the p-type FinFET.

4. The semiconductor device according to claim 1, wherein the fin width of the channel region of the p-type FinFET is equal to the fin width of the channel region of the n-type FinFET.

5. The semiconductor device according to claim 1, wherein the impurity concentration of the channel region of the p-type FinFET is higher than the impurity concentration of the channel region of the n-type FinFET.

6. The semiconductor device according to claim 1, further comprising an n-well region provided in the semiconductor substrate,

wherein the p-type FinFET is provided in the n-well region and a bias voltage is applied to the n-well region.

7. The semiconductor device according to claim 1, wherein the semiconductor substrate is composed of an SOI region and a bulk region and the n-type FinFET is arranged in the SOI region and the p-type FinFET is arranged in the bulk region.

8. The semiconductor device according to claim 1, wherein the channel plane of the n-type FinFET is an Si (100) plane and the channel plane of the p-type FinFET is an Si (110) plane.

9. A semiconductor device comprising:

a semiconductor substrate;

a first gate electrode provided on the semiconductor substrate;

a first n-type FinFET which includes a first fin acting as an active region provided on the semiconductor substrate, a first channel region provided in the first fin in a place where the first gate electrode crosses the first fin via a gate insulating film in three dimensions, and first contact regions provided at one end and the other end of the first fin and sandwiching the first channel region;

a first p-type FinFET which includes a second fin acting as an active region provided on the semiconductor substrate, a second channel region provided in the second fin in the place where the first gate electrode crosses the second fin via a gate insulating film in three dimensions, and second contact regions provided at one end and the other end of the second fin and sandwiching the second channel region;

a second gate electrode provided on the semiconductor substrate;

a second n-type FinFET which includes a third fin acting as an active region provided on the semiconductor substrate, a third channel region provided in the third fin in a place where the second gate electrode crosses the third fin via a gate insulating film in three dimensions, and third contact regions provided at one end and the other end of the third fin and sandwiching the third channel region;

a second p-type FinFET which includes a fourth fin acting as an active region provided on the semiconductor substrate, a fourth channel region provided in the fourth fin in a place where the second gate electrode crosses the fourth fin via a gate insulating film in three dimensions, and fourth contact regions provided at one end and the other end of the fourth fin and sandwiching the fourth channel region;

a first output node which is a node between the first contact region at one end of the first fin and the second contact region at one end of the second fin and is connected to the second gate electrode;

a second output node which is a node between the third contact region at one end of the third fin and the fourth contact region at one end of the fourth fin and is connected to the first gate electrode;

a third n-type FinFET which includes a fifth fin acting as an active region provided on the semiconductor substrate, a third gate electrode which crosses a fifth channel region of the fifth fin via a gate insulating film in three dimensions, and fifth contact regions provided at one end and the other end of the fifth fin and sandwiching the fifth channel region, one of the fifth contact regions being connected to the first output node;

a fourth n-type FinFET which includes a sixth fin acting as an active region provided on the semiconductor substrate, a forth gate electrode which crosses a sixth channel region of the sixth fin via a gate insulating film in three dimensions, and sixth contact regions provided at one end and the other end of the sixth fin and sandwiching the sixth channel region, one of the sixth contact regions being connected to the second output node,

wherein the fin width of the second and fourth contact regions constituting the first and second output nodes respectively is greater than the fin width of the first and third channel regions.

10. The semiconductor device according to claim 9, wherein the first gate electrode is in contact with the fourth contact region constituting the second output node, and

the second gate electrode is in contact with the second contact region constituting the first output node.

11. The semiconductor device according to claim 9, wherein the fin width of the second and fourth channel regions is greater than the width of the first and third channel regions.

12. The semiconductor device according to claim 9, wherein the fin width of the second and fourth contact regions is greater than the fin width of the second and fourth channel regions.

13. The semiconductor device according to claim 9, wherein the fin width of the second and fourth channel regions is equal to the fin width of the first and third channel regions.

14. The semiconductor device according to claim 9, wherein the impurity concentration of the second and fourth channel regions is higher than the impurity concentration of the first and third channel regions.

15. The semiconductor device according to claim 9, further comprising an n-well region provided in the semiconductor substrate,

wherein the first and second p-type FinFETs are provided in the n-well region and a bias voltage is applied to the n-well region.

16. The semiconductor device according to claim 9, wherein the semiconductor substrate is composed of an SOI region and a bulk region and the n-type FinFET is arranged in the SOI region and the p-type FinFET is arranged in the bulk region.

17. The semiconductor device according to claim 9, wherein the channel plane of the n-type FinFET is an Si (100) plane and the channel plane of each of the first and second p-type FinFET is an Si (110) plane.

18. The semiconductor device according to claim 9, wherein the first and fifth fins are provided in a same projecting semiconductor region.

19. The semiconductor device according to claim 18, wherein the first and fifth contact regions provided between the first channel region and the fifth channel region are shared by the first and fifth n-type FinFETs as a single common contact region.

20. The semiconductor device according to claim 9, further comprising:

a seventh n-type FinFET which includes a seventh fin acting as an active region provided on the semiconductor substrate so as to adjoin the first fin, a seventh channel region provided in the seventh fin in a place where the first gate electrode crosses the seventh fin via a gate insulating film in three dimensions, and seventh contact regions provided at one end and the other end of the seventh fin and sandwiching the seventh channel region; and

an eighth n-type FinFET which includes an eighth fin acting as an active region provided on the semiconductor substrate so as to adjoin the third fin, an eighth channel region provided in the eight fin in a place where the second gate electrode crosses the eighth fin via a gate insulating film in three dimensions, and eighth contact regions provided at one end and the other end of the eighth fin and sandwiching the eighth channel region,

wherein the seventh contact regions provided at one end and the other end of the seventh fin respectively are connected to the first contact regions provided at one end and the other end of the first fin, and

the eighth contact regions provided at one end and the other end of the eighth fin respectively are connected to the third contact regions provided at one end and the other end of the third fin.