Memory with correlated resistance
First Claim
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1. A method of operating a memory device, comprising:
- writing a plurality of data values to a plurality of data locations, wherein the plurality of data locations are coupled to one another in a series, and wherein the plurality of data values are sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location.
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Abstract
Methods, systems, and devices are disclosed, such as a method of operating a memory device. In certain embodiments, such a method includes writing a plurality of data values to a plurality of data locations. The plurality of data locations may be coupled to one another in a series, and the plurality of data values may be sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location.
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Citations
24 Claims
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1. A method of operating a memory device, comprising:
writing a plurality of data values to a plurality of data locations, wherein the plurality of data locations are coupled to one another in a series, and wherein the plurality of data values are sequentially written to the plurality of data locations, starting with the data location at an end of the series and then sequentially writing to each adjacent data location. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A system, comprising:
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a plurality of floating gate transistors coupled in series source-to-drain; and a controller configured to write to each of the plurality of floating gate transistors in sequence such that, for each of the plurality of floating gate transistors, source-side floating gate transistors are written to first. - View Dependent Claims (14, 15, 16, 17)
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18. A method of operating an integrated semiconductor device, comprising:
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erasing a plurality of floating gate transistors coupled to each other in a series source-to-drain; writing to each of the plurality of floating gate transistors one at a time, in sequence, starting with a floating gate transistor at an end of the series and finishing with a floating gate transistor at the other end of the series. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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Specification