IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME

• US 20080315252A1
• Filed: 12/31/2007
• Published: 12/25/2008
• Est. Priority Date: 06/25/2007
• Status: Active Grant

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Shim, Cheon Man
• Granted Patent: US 7,728,351 B2
• Time in Patent Office: Days
• US Class Current: 257/184
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14692 Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Abstract

An image sensor provides enhanced integration of transistor circuitry and photo diodes. The image sensor simultaneously improves resolution and sensitivity. An image sensor an a method for manufacturing prevents defects in a photo diode by adopting a vertical photo diode structure. An image sensor includes a substrate which may include at least one circuit element. A bottom electrode and a first conductive layer may be sequentially formed over the substrate. A strained intrinsic layer may be formed over the first conductive layer. A second conductive layer may be formed over the strained intrinsic layer. An upper electrode may be formed over the second conductive layer.

Claims

1. An apparatus comprising:

a substrate including at least one circuit element;

a bottom electrode and a first conductive layer sequentially formed over the substrate;

a strained intrinsic layer formed over the first conductive layer;

a second conductive layer formed over the strained intrinsic layer; and

an upper electrode formed over the second conductive layer.

2. The apparatus of claim 1, wherein the first conductive layer is a first conductive silicon-germanium layer.

3. The apparatus of claim 1, wherein the lattice constant for the strained intrinsic layer is smaller than the lattice constant for the first conductive layer.

4. The apparatus of claim 1, wherein the strained intrinsic layer is a strained silicon intrinsic layer.

5. The apparatus of claim 4, wherein the second conductive layer is a second conductive silicon layer.

6. The apparatus of claim 4, wherein the second conductive layer is a second conductive silicon-germanium layer.

7. The apparatus of claim 1, further comprising a first conductive silicon layer formed between the bottom electrode and the first conductive layer.

8. The apparatus of claim 1, wherein the upper electrode is transparent.

9. The apparatus of claim 1, wherein the upper electrode is formed of one of indium tin oxide and cadmium tin oxide.

10. The apparatus of claim 1, wherein the layers collectively comprise components of a CMOS image sensor.

11. An apparatus comprising:

a substrate including at least a first circuit element;

a bottom electrode formed over the substrate;

a silicon-germanium intrinsic layer formed over the bottom electrode;

a second conductive layer formed over the silicon-germanium intrinsic layer; and

an upper electrode formed over the second conductive layer.

12. The apparatus of claim 11, further comprising a first conductive silicon-germanium layer formed over the bottom electrode.

13. The apparatus of claim 11, wherein the second conductive layer is a second conductive silicon-germanium layer.

14. The apparatus of claim 11, further comprising a first conductive silicon layer formed between the bottom electrode and the first conductive layer.

15. The apparatus of claim 11, wherein the upper electrode is transparent.

16. A method comprising:

sequentially forming a bottom electrode and a first conductive layer over a substrate including at least one circuit element;

forming a strained intrinsic layer over the first conductive layer;

forming a second conductive layer over the stained intrinsic layer; and

forming an upper electrode over the second conductive layer.

17. The method of claim 16, wherein the first conductive layer is a first conductive silicon-germanium layer.

18. The method of claim 17, wherein the strained intrinsic layer is a strained silicon intrinsic layer.

19. The method of claim 16, wherein the strained intrinsic layer is a strained silicon intrinsic layer.

20. The method of claim 16, wherein the upper electrode is transparent.