BIAS CIRCUITS AND METHODS FOR ENHANCED RELIABILITY OF FLASH MEMORY DEVICE

• US 20080316834A1
• Filed: 08/29/2008
• Published: 12/25/2008
• Est. Priority Date: 06/27/2005
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lim, Young-Ho, Chae, Dong-Hyuk
• Granted Patent: US 7,619,929 B2
• Time in Patent Office: Days
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

Claims

1. A non-volatile semiconductor memory device comprising:

cell strings connected to respective bit lines;

each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor;

a charge pump and voltage regulator configured to supply a substantially constant read voltage; and

a string select line driver circuit configured to drive the string select line with a first voltage which is lower than the read voltage.

2. The non-volatile semiconductor memory device of claim 1, wherein the string select line driver circuit comprising:

a first voltage generating circuit configured to generate the first voltage which is lower than the read voltage during a read operation; and

a first high voltage switch configured to output the first voltage in response to a read enable signal.

3. The non-volatile semiconductor memory device of claim 1, wherein the device further comprising:

a ground select line driver circuit configured to drive the ground select line with a second voltage which is lower than the read voltage.

4. The non-volatile semiconductor memory device of claim 3, wherein the ground select line driver circuit comprising:

a second voltage generating circuit configured to generate the second voltage which is lower than the read voltage during the read operation; and

a second high voltage switch configured to output the second voltage in response to the read enable signal.

5. The non-volatile semiconductor memory device of claim 4, wherein the first voltage provided by the first voltage generating circuit is the same as the second voltage provided by the second voltage generating circuit.

6. The non-volatile semiconductor memory device of claim 4, wherein the first voltage provided by the first voltage generating circuit is higher than the second voltage provided by the second voltage generating circuit.

7. The non-volatile semiconductor memory device of claim 4, wherein the first voltage provided by the first voltage generating circuit is lower than the second voltage provided by the second voltage generating circuit.

8. The non-volatile semiconductor memory device of claim 2, wherein the first voltage generating circuit is configured to generate the first voltage which is lower than the read voltage by 2Vth, where Vth is a threshold voltage of an NMOS transistor.

9. The non-volatile semiconductor memory device of claim 4, wherein the second voltage generating circuit is configured to generate the second voltage which is lower than the read voltage by 2Vth, where Vth is a threshold voltage of an NMOS transistor.

10. The non-volatile semiconductor memory device of claim 2, wherein the first voltage generating circuit is configured to generate the first voltage which is lower than the read voltage by N*Vth, where N is an integer and Vth is a threshold voltage of an NMOS transistor.

11. The non-volatile semiconductor memory device of claim 4, wherein the second voltage generating circuit is configured to generate the second voltage which is lower than the read voltage by N*Vth, where N is an integer and Vth is a threshold voltage of an NMOS transistor.

12. A non-volatile semiconductor memory device having a plurality of memory blocks each including first transistors for selecting a plurality of word lines and second transistors for selecting string select lines and ground select lines, the device further comprising:

a charge pump configured to generate a read voltage during a read operation;

a voltage regulator configured to control the charge pump so that the read voltage is maintained at a substantially constant level;

a first driver circuit configured to transfer the read voltage to the first transistors during the read operation;

a voltage generating circuit configured to generate a select voltage which is lower than the read voltage;

at least one second driver circuit configured to drive the string select lines and ground select lines with the select voltage during the read operation; and

at least one high voltage switch configured to output the select voltage from the at least one second driver circuit to the second transistors during the read operation in response to a read enable signal.

13. The non-volatile semiconductor memory device of claim 12, wherein the voltage generating circuit generates the select voltage which is lower than the read voltage by a voltage that corresponds to a sum of threshold voltages of plural transistors.

14. The non-volatile semiconductor memory device of claim 12, wherein the voltage generating circuit includes first and second voltage generating portions for generating a first and a second voltage each, the first voltage being applied to the string select line by the second driver circuit and the second voltage being applied to the ground select line by the second driver circuit.

15. The non-volatile semiconductor memory device of claim 14, wherein the first voltage is higher than the second voltage.

16. The non-volatile semiconductor memory device of claim 14, wherein the first voltage is lower than the second voltage.

17. The non-volatile semiconductor memory device of claim 14, wherein each of the first and second voltage generating parts is configured to generate the first and the second voltages which are lower than the read voltage by 2Vth, where Vth is a threshold voltage of an NMOS transistor.

18. A read voltage supplying method in a non-volatile semiconductor memory device which comprises cell strings connected to respective bit lines, each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected between the select transistors and connected to corresponding word lines, the method comprising:

generating a substantially constant read voltage to be supplied to unselected word lines;

supplying a first voltage which is lower than the read voltage to the string select lines in response to a control signal indicating a read operation; and

supplying the read voltage to the unselected word lines in response to the control signal.

19. The method of claim 18, wherein the method further comprising:

supplying a second voltage which is lower than the read voltage to the ground select lines in response to a control signal indicating a read operation.

20. A non-volatile semiconductor memory device comprising:

cell strings connected to respective bit lines;

each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor;

a charge pump and voltage regulator configured to supply a substantially constant read voltage;

a first voltage generating circuit configured to generate a first voltage which is lower than the read voltage during a read operation;

a second voltage generating circuit configured to generate a second voltage which is lower than the read voltage during a read operation;

a string select line driver circuit configured to drive the string select line with the first voltage provided by the first voltage generating circuit during a read operation in response to a read enable signal; and

a ground select line driver circuit configured to drive a ground select line with the second voltage provided by the second voltage generating circuit during a read operation in response to the read enable signal.