METHODS OF FORMING HIGH DENSITY SEMICONDUCTOR DEVICES USING RECURSIVE SPACER TECHNIQUE

• US 20080318381A1
• Filed: 06/20/2007
• Published: 12/25/2008
• Est. Priority Date: 06/20/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Mokhlesi, Nima, Kai, James, Orimoto, Takashi, Matamis, George
• Granted Patent: US 8,143,156 B2
• Time in Patent Office: Days
• US Class Current: 438/264
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.

Claims

1. A method of controlling the length, orthogonal to a reference plane, of a plurality of conductive gate regions on a substrate, and the spacing between the plurality of conductive gate regions, the method comprising the steps of:

(a) lithographically forming a plurality of strips on the substrate, the plurality of strips having a length parallel to the reference plane, and a spacing between a plurality of strips, defined for the purpose of controlling the length and spacing of the plurality of conductive gate regions, the plurality of strips including sidewalls substantially orthogonal to the reference plane;

(b) forming a first plurality of spacers on the sidewalls of the plurality of strips, the first plurality of spacers having a length, orthogonal to the reference plane, defined for the purpose of controlling the length and spacing of the plurality of conductive gate regions;

(c) processing the first plurality of spacers to provide a plurality of structures with first and second sidewalls that are;

     1) planar,

     2) parallel to each other, and

     3) orthogonal to the reference plane; and

(d) forming the second plurality of spacers on the sidewalls of the plurality of structures, the second plurality of spacers having a length, orthogonal to the reference plane, defined for the purpose of controlling the length and spacing of the plurality of conductive gate regions, the second set of spacers forming a mask defining the length and spacing of the plurality of conductive gate regions.

2. A method as recited in claim 1, wherein the length of the conductive gate regions is approximately 30 nm and the spacing between the conductive gate regions is approximately 30 nm.

3. A method as recited in claim 2, wherein said step (a) comprises the step of selecting the first plurality of strips to be approximately 90 nm and spaced from each other approximately 150 nm.

4. A method as recited in claim 3, wherein said step (b) comprises the step of selecting the first plurality of spacers to have a length of 30 nm.

5. A method as recited in claim 4, wherein said step (d) comprises the step of selecting the second plurality of spacers to have a length of 30 nm.

6. A method as recited in claim 1, wherein said step (c) of processing the first plurality of spacers to provide the plurality of structures with planar and parallel sidewalls comprises the steps of:

(c1) filling in gaps between the first plurality of spacers on the plurality of strips; and

(c2) polishing down the first plurality of spacers to remove rounded edges and to form the first plurality of spacers into the plurality of structures with planar and parallel sidewalls.

7. A method as recited in claim 6, wherein said step (c2) comprises the step of chemical-mechanical polishing.

8. A method as recited in claim 1, wherein said step (c) of processing the first plurality of spacers to provide the plurality of structures with planar and parallel sidewalls comprises the step of using the first plurality of spacers as a mask to form the structures with planar and parallel sidewalls in a layer beneath the first plurality of spacers.

9. A method of forming an integrated semiconductor device, comprising the steps of:

(a) defining a plurality of strips of a first material on a layer formed on a substrate, the plurality of strips including sidewalls substantially orthogonal to the layer formed on the substrate;

(b) depositing a second material on each pair of sidewalls of the plurality of sidewalls;

(c) etching the second material to define a first set of spacers on sidewalls of the plurality of strips, gaps being defined between spacers of adjacent strips of the plurality of strips;

(d) depositing a third material over the plurality of strips and first set of spacers, and in the gaps between spacers;

(e) polishing down the third material, the strips and the first set of spacers to define a planar surface;

(f) etching the plurality of strips and third material in the gaps to expose sidewalls on the first set of spacers, the sidewalls of the first set of spacers being substantially orthogonal to the layer formed on the substrate;

(g) depositing a fourth material on the sidewalls of the first set of spacers;

(h) etching the fourth material to define a second set of spacers on the sidewalls of the first set of spacers; and

(i) etching the first set of spacers to leave the second set of spacers, the second set of spacers forming a mask for defining elements in a layer beneath the second set of spacers.

10. A method as recited in claim 9, wherein said step (a) comprises the step of defining the first plurality of strips to strips of approximately 90 nm and spaced from each other 150 nm.

11. A method as recited in claim 10, wherein said step (c) comprises the step of etching the second material to define the first set of spacers each having a length orthogonal to the layer defined in said step (a) of 30 nm.

12. A method as recited in claim 11, wherein said step (h) comprises the step of etching the fourth material to define the second set of spacers each having a length orthogonal to the layer defined in said step (a) of 30 nm.

13. A method as recited in claim 9, wherein the first material and third material are the same material.

14. A method as recited in claim 9, wherein the first material is silicon oxide.

15. A method as recited in claim 9, wherein the second material is silicon nitride.

16. A method as recited in claim 9, wherein the fourth material is polysilicon.

17. A method as recited in claim 9, wherein said step (e) of polishing comprises a chemical-mechanical polishing.

18. A method as recited in claim 9, further comprising the step of using the second set of spacers as a mask to define a plurality of conductive gate regions on the substrate.

19. A method of forming an integrated semiconductor device, comprising the steps of:

(a) forming a first sacrificial layer on a substrate, the first sacrificial layer defining a reference plane;

(b) forming a second sacrificial layer over the first sacrificial layer;

(c) defining a first plurality of strips in the first sacrificial layer, the first plurality of strips including sidewalls substantially orthogonal to the reference plane;

(d) defining a first set of spacers on the sidewalls of the first plurality of strips, each spacer of the first set of spacers having a first, straight surface in contact with a sidewall, and a second, curved surface opposed to the first surface;

(e) defining a second plurality of strips in the second sacrificial layer using the first set of spacers defined in said step (d) as a mask, the second plurality of strips including sidewalls having portions orthogonal to the reference plane; and

(f) defining a second set of spacers on the orthogonal portions of the second plurality of strips, the second set of spacers forming a mask for defining elements in a layer beneath the second set of spacers.

20. A method as recited in claim 19, wherein the first sacrificial layer is silicon oxide.

21. A method as recited in claim 19, wherein the second sacrificial layer is silicon oxide.

22. A method as recited in claim 19, wherein the first and second sacrificial layers are silicon oxide.

23. A method as recited in claim 19, wherein the first set of spacers is silicon nitride.

24. A method as recited in claim 19, wherein the second set of spacers is polysilicon.

25. A method as recited in claim 19, further comprising the step of using the second set of spacers as a mask to define a plurality of conductive gate regions on the substrate.