STRESS ENHANCED MOS CIRCUITS

• US 20090001476A1
• Filed: 09/10/2008
• Published: 01/01/2009
• Est. Priority Date: 08/11/2006
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: PEI, Gen
• Granted Patent: US 7,943,999 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/28061 the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction H01L21/28052 takes precedence
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

A stress enhanced MOS circuit is provided. The stress enhanced MOS circuit comprises a semiconductor substrate and a gate insulator overlying the semiconductor substrate. A gate electrode overlies the gate insulator; the gate electrode has side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness overlying the layer of polycrystalline silicon. A stress liner overlies the side walls of the gate electrode.

Claims

1. A stress enhanced MOS circuit, comprising:

a semiconductor substrate;

a gate insulator overlying the semiconductor substrate;

a gate electrode overlying the gate insulator, the gate electrode having side walls and comprising a layer of polycrystalline silicon having a first thickness in contact with the gate insulator and a layer of electrically conductive stressed material having a second thickness greater than the first thickness, the layer of electrically conductive stressed material overlying and contacting the layer of polycrystalline silicon; and

a stress liner layer overlying the side walls.

2. The MOS circuit of claim 1 wherein the second thickness is at least five times the first thickness.

3. The MOS circuit of claim 1 wherein the electrically conductive stressed material comprises titanium nitride.

4. The MOS circuit of claim 3 wherein the stress liner layer comprises silicon nitride.

5. The MOS circuit of claim 1 wherein the electrically conductive stressed material comprises a tensile stressed material.

6. The MOS circuit of claim 5 wherein the stress liner layer comprises a compressive stressed material.

7. The MOS circuit of claim 5 wherein the tensile stressed material has a tensile stress of at least approximately 2.0 GPa.

8. The MOS circuit of claim 3 wherein the titanium nitride has a compressive stress greater than approximately −

2.5 GPa.

9. The MOS circuit of claim 8 wherein the titanium nitride has a compressive stress of approximately −

10 GPa.

10. The MOS circuit of claim 1 wherein the electrically conductive stressed material comprises compressive stressed material.

11. The MOS circuit of claim 10 wherein the stress liner layer comprises a tensile stressed material.

12. The MOS circuit of claim 4 wherein the silicon nitride has a tensile stress of about 1.2 GPa.

13. A stress enhanced NMOS circuit, comprising:

a semiconductor substrate;

a gate insulator overlying the semiconductor substrate;

a gate electrode overlying the gate insulator, the gate electrode having side walls and comprising a layer of gate electrode forming material in contact with the gate insulator and a layer of electrically conductive compressive stressed material overlying and contacting the layer of gate electrode forming material; and

a tensile stress liner layer overlying the side walls.

14. The NMOS circuit of claim 13 wherein the electrically conductive compressive stressed material comprises titanium nitride having a compressive stress greater than approximately −

2.5 GPa.

15. The NMOS circuit of claim 14 wherein the titanium nitride has a compressive stress of approximately −

10 GPa.

16. The NMOS circuit of claim 13 wherein the thickness of the electrically conductive compressive stressed material is at least five times the thickness of the layer of gate electrode forming material.

17. The NMOS circuit of claim 13 wherein tensile stress liner layer comprises silicon nitride.

18. The NMOS circuit of claim 17 wherein the silicon nitride has a tensile stress of approximately 1.2 GPa.

19. A stress enhanced PMOS circuit, comprising:

a semiconductor substrate;

a gate insulator overlying the semiconductor substrate;

a gate electrode overlying the gate insulator, the gate electrode having side walls and comprising a layer of gate electrode forming material in contact with the gate insulator and a layer of electrically conductive tensile stressed material overlying and contacting the layer of gate electrode forming material; and

a compressive stress liner layer overlying the side walls.

20. The stress enhanced PMOS of claim 19 wherein electrically conductive tensile stressed material has a tensile strength greater than approximately 2.0 GPa.