DUAL BIT LINE METAL LAYERS FOR NON-VOLATILE MEMORY

• US 20090003025A1
• Filed: 06/26/2007
• Published: 01/01/2009
• Est. Priority Date: 06/26/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Wan, Jun, Mokhlesi, Nima
• Granted Patent: US 8,368,137 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4 f pitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.

Claims

1. A non-volatile storage device, comprising:

a plurality of non-volatile storage elements formed on a semiconductor substrate;

a plurality of bit lines alternately formed in at least two separate metal layers over the semiconductor substrate; and

a plurality of connections between the bit lines and the storage elements.

2. The non-volatile storage device of claim 1, wherein the bit lines are formed at a pitch of 4 f in each of the metal layers.

3. The non-volatile storage device of claim 1, further comprising:

a plurality of shields formed in each of the separate metal layers between each bit line.

4. The non-volatile storage device of claim 3, wherein each of the shields formed in a first of the metal layers is connected to a ground potential and each of the shields formed in a second of the metal layers is connected to a source potential.

5. The non-volatile storage device of claim 3, wherein each of the shields is formed in segments between the connections.

6. The non-volatile storage device of claim 5, wherein each of the connections is formed in regular intervals relative to the storage elements.

7. The non-volatile storage device of claim 5, wherein the storage elements are organized into blocks, and one connection is formed for every two blocks of storage elements.

8. A non-volatile storage device, comprising:

a plurality of non-volatile storage elements formed in an array on a semiconductor substrate;

a first plurality of bit lines formed in parallel in a first metal layer over the array; and

a second plurality of bit lines formed in parallel in a second metal layer over the first metal layer; and

a plurality of connections between the bit lines and the storage elements,

wherein each of the first and second plurality of bit lines is formed to alternate between the first and second metal layers relative to the storage elements.

9. The non-volatile storage device of claim 8, wherein the array is organized into rows and columns of storage elements, and wherein adjacent columns are connected to respective bit lines in different metal layers.

10. The non-volatile storage device of claim 8, further comprising:

a plurality of shields formed in each metal layer between each adjacent pair of bit lines.

11. The non-volatile storage device of claim 10, further comprising:

a first plurality of shields formed in the first metal layer such that each shield is formed between a pair of the first plurality of bit lines; and

a second plurality of shields formed in the second metal layer such that each shield is formed between a pair of the second plurality of bit lines.

12. The non-volatile storage device of claim 11, wherein each of the first plurality of shields is connected to a ground potential, and each of the second plurality of shields is connected to a source potential.

13. A non-volatile storage system, comprising:

a plurality of non-volatile storage elements formed in an array on a semiconductor substrate, said array being organized into rows and columns;

a first plurality of bit lines formed in a first metal layer over the array in correspondence with a first set of columns comprising every other column;

a second plurality of bit lines formed in a second metal layer over the first metal layer in correspondence with a second set of columns comprising every other column not in the first set of columns; and

a plurality of connections between the bit lines and the storage elements such that adjacent columns are connected to bit lines in different metal layers.

14. The non-volatile storage system of claim 13, further comprising:

a plurality of shields formed in each of the metal layers between each bit line.

15. The non-volatile storage system of claim 14, wherein the bit lines and shields are formed at a pitch of 2 f relative to each other in each of the metal layers.

16. The non-volatile storage system of claim 14, wherein each of the shields is formed in segments between the connections.

17. The non-volatile storage system of claim 16, wherein each of the bit lines is formed to be wider between connections and narrower proximate to each connection.

18. The non-volatile storage system of claim 14, wherein the metal layers are formed to be approximately 80 nanometers thick, and dielectric layers are formed between each metal layer to be approximately 250 nanometers thick.

19. The non-volatile storage system of claim 18, wherein the bit lines are formed to be approximately 60 nanometers wide, and spaced apart by a lateral distance of approximately 220 nanometers on center, in each metal layer.

20. The non-volatile storage system of claim 18, wherein the lateral distance between adjacent alternating bit lines is approximately 110 nanometers on center.