Method of Integration of a MIM Capacitor with a Lower Plate of Metal Gate Material Formed on an STI Region or a Silicide Region Formed in or on the Surface of a Doped Well with a High K Dielectric Material
1-20. -20. (canceled)
A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.
1-20. -20. (canceled)
21. A method of forming an integrated MIM capacitor, comprising the steps of:
providing a semiconductor substrate having a top surface; forming a lower capacitor plate and a High K (HiK) dielectric layer consisting of a material selected from the group consisting of Ta2O5, BaTiO3, HfO2, ZrO2, and Al2O3;
by the step comprising;
(i) forming a doped well in said surface of said semiconductor substrate, then forming a silicide region, in said surface of said doped well followed by forming said High K (HiK) dielectric layer on said surface of said silicide region; (ii) forming a doped well in said surface of said semiconductor substrate, followed by forming said HiK dielectric layer on said surface of said doped well;
(iii) forming a Shallow Trench Isolation (STI) region in said semiconductor substrate below said surface of said semiconductor substrate followed by forming a conductor layer overlying said STI region, and then followed by forming said HiK dielectric film over said conductor layer; and forming a second capacitor plate over said HiK dielectric film above said lower capacitor plate.
- View Dependent Claims (22, 23, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
23-1. A method in accordance with claim 22 wherein said first capacitor HiK dielectric layer consists of a material selected from the group consisting of Ta2O5, BaTiO3, HfO2, ZrO2, and Al2O3.