Method of Integration of a MIM Capacitor with a Lower Plate of Metal Gate Material Formed on an STI Region or a Silicide Region Formed in or on the Surface of a Doped Well with a High K Dielectric Material

• US 20090004809A1
• Filed: 01/08/2008
• Published: 01/01/2009
• Est. Priority Date: 09/12/2005
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: He, Zhong-Xiang, Eshun, Ebenezer E., Stamper, Anthony Kendall, Vaed, Kunal, Coolbaugh, Douglas Duane, Chinthakindi, Anil Kumar, Rassel, Robert Mark, Downes, Keith Edward
• Granted Patent: US 7,915,134 B2
• Time in Patent Office: Days
• US Class Current: 438/393
• CPC Class Codes: H01L 28/40 Capacitors

Abstract

A MIM capacitor is formed on a semiconductor substrate having a top surface and including regions formed in the surface selected from a Shallow Trench Isolation (STI) region and a doped well having exterior surfaces coplanar with the semiconductor substrate. A capacitor lower plate is either a lower electrode formed on the STI region in the semiconductor substrate or a lower electrode formed by a doped well formed in the top surface of the semiconductor substrate that may have a silicide surface. A capacitor HiK dielectric layer is formed on or above the lower plate. A capacitor second plate is formed on the HiK dielectric layer above the capacitor lower plate. A dual capacitor structure with a top plate may be formed above the second plate with vias connected to the lower plate protected from the second plate by side wall spacers.

Claims

1-20. -20. (canceled)

21. A method of forming an integrated MIM capacitor, comprising the steps of:

providing a semiconductor substrate having a top surface;

forming a lower capacitor plate and a High K (HiK) dielectric layer consisting of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃;

by the step comprising;

(i) forming a doped well in said surface of said semiconductor substrate, then forming a silicide region, in said surface of said doped well followed by forming said High K (HiK) dielectric layer on said surface of said silicide region;

(ii) forming a doped well in said surface of said semiconductor substrate, followed by forming said HiK dielectric layer on said surface of said doped well;

or

(iii) forming a Shallow Trench Isolation (STI) region in said semiconductor substrate below said surface of said semiconductor substrate followed by forming a conductor layer overlying said STI region, and then followed by forming said HiK dielectric film over said conductor layer; and

forming a second capacitor plate over said HiK dielectric film above said lower capacitor plate.

22. A method in accordance with claim 21 comprising:

forming a second capacitor HiK dielectric layer on said second plate electrode; and

forming a top capacitor plate on said second capacitor HiK dielectric layer above said second plate electrode; and

connecting said lower capacitor plate electrically to said top capacitor plate;

whereby a dual capacitor with dual. HiK integration is provided.

23. A method of forming an integrated Metal Insulator-Metal (MIM) capacitor on a semiconductor substrate comprising:

forming a base comprising a semiconductor substrate having a top surface and including regions formed in said surface having exterior surfaces coplanar with said semiconductor substrate selected from a doped P/N well and a Shallow French Isolation (STI) region;

forming a lower capacitor plate selected from the group comprising a silicide electrode layer formed in said top surface of said doped P/N well; and

a lower electrode formed on said STI region in said semiconductor substrate;

forming a first capacitor High K (HiK) dielectric layer on said lower capacitor plate, and

forming a second capacitor plate layer patterned into a second capacitor plate on said HiK dielectric layer above said lower capacitor plate.

25. The method of claim 22 wherein:

said lower capacitor plate comprises a said silicide layer formed in said surface of said substrate in said doped well;

said first capacitor HiK dielectric layer is formed on said top surface of said silicide layer in said doped well; and

said capacitor second plate is formed on said first capacitor HiK dielectric layer above said lower capacitor plate including said silicide layer in said doped well.

26. A method in accordance with claim 25 wherein said first capacitor HiK dielectric layer consists of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃.

27. The method of claim 23 wherein:

said lower capacitor plate comprises a said silicide layer formed in said surface of said substrate in said doped well;

said first capacitor Hill dielectric layer is formed, on said top surface of said silicide layer in said doped well; and

said capacitor second plate layer is formed on said first capacitor HiK dielectric layer above said lower capacitor plate including said silicide layer in said doped well;

forming an etch stop layer over said capacitor second plate;

patterning said etch stop layer, said capacitor second plate layer, and said first and second HiK dielectric layers thereby forming a capacitor second plate;

forming holes through said etch stop layer;

forming vias to said lower capacitor plate and a capacitor second, plate; and

forming metallization, connected to said, vias; and

said first and second capacitor HiK dielectric layers consist of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂ and Al₂O₃.

28. The method of claim 23 wherein:

said lower capacitor plate comprises a said silicide layer formed in said top surface of said substrate in said doped well;

said first HiK dielectric layer is formed on said top surface of said substrate on said silicide layer in said doped well;

said second capacitor plate comprises an electrode layer formed on said first HiK dielectric layer;

forming a second capacitor HiK dielectric layer on said second capacitor plate;

forming a top capacitor plate on said second capacitor HiK dielectric layer over said lower capacitor plate; and

connecting said lower capacitor plate electrically to said top capacitor plate;

whereby a dual MIM-metal/HiK gate integration, is provided over a region of diffused dopant in said substrate.

29. A method in accordance with claim 28 wherein said first capacitor HiK dielectric layer consists of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃.

30. The method of claim 23 wherein:

said substrate includes a said STI region;

said lower capacitor plate comprises a said lower electrode formed on top of said STI region composed of a material selected from a metal layer and a polysilicon layer capped with a silicide layer;

said first capacitor HiK dielectric layer is formed on said lower capacitor plate; and

said capacitor second plate is formed on said first capacitor HiK dielectric layer above said metal electrode.

31. A method in accordance with claim 32 wherein said first capacitor HiK dielectric layer consists of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃.

32. The method of claim 23 wherein:

said lower capacitor plate comprises a said silicide layer formed in said top surface of said substrate in said doped well;

said first HiK dielectric layer is formed on said top surface of said substrate on said silicide layer in said, doped well;

said second capacitor plate comprises an electrode layer formed on said first HiK dielectric layer;

forming a second capacitor HiK dielectric layer on said second capacitor plate,

patterning said second capacitor plate and said second capacitor HiK dielectric layers to form a capacitor second plate;

forming a top capacitor plate layer on said second capacitor HiK dielectric layer over said lower capacitor plate;

forming an etch stop layer over said top capacitor plate layer;

patterning said etch stop layer and said top capacitor plate layer to form, a top capacitor plate;

forming holes through said etch stop layer;

forming vias to said lower capacitor plate, said a capacitor second plate and said top capacitor plate, and

forming metallization connected to said vias connecting said lower capacitor plate electrically to said top capacitor plate;

whereby a dual MIM-metal/HiK gate integration is provided over a region of diffused dopant, in said substrate.

33. A method in accordance with claim 30 wherein said first capacitor HiK dielectric layer consists of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃.

34. The method of claim 23 wherein steps are performed in the sequence as follows:

forming said lower capacitor plate composed of a metal layer on top of said STI region;

patterning said metal layer to form a lower metal electrode;

forming sidewall spacers on said lower metal electrode;

forming said first HiK dielectric layer is on top of said lower metal electrode;

forming said capacitor second plate on said first HiK dielectric layer;

forming an etch stop layer;

patterning said etch stop layer and said capacitor second plate;

forming vias to said lower capacitor plate and said capacitor second plate, and

forming metallization connected to said vias.

35. A method in accordance with claim 34 wherein said first capacitor HiK dielectric layer consists of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃.

36. The method of claim 23 wherein steps are performed in the sequence as follows:

forming said lower electrode composed of polysilicon on top of said STI region;

said first HiK dielectric layer is formed on top of said silicided polysilicon formed on top of said STI regions;

said capacitor second plate is formed on said first HiK dielectric layer;

forming a second capacitor HiK dielectric layer on said capacitor second plate;

forming a top capacitor plate on said second capacitor HiK dielectric layer over said lower capacitor plate including said silicide layer and said doped polysilicon layer; and

connecting said lower capacitor plate electrically to said top capacitor plate;

whereby said lower capacitor plate comprises a said lower electrode composed of si lidded polysilicon formed on top of said STI region.

37. A method in accordance with claim 36 wherein said first capacitor HiK dielectric layer consists of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃.

38. The method of claim 32 wherein:

said substrate includes a said STI region;

said lower capacitor plate comprises a silicided, doped polysilicon layer formed on said STI region; and

said first capacitor HiK dielectric layer is formed on said lower capacitor plate; and

said top capacitor plate is formed on said first capacitor HiK dielectric layer above said silicide layer and said polysilicon layer.

39. The method of claim 38 wherein said lower capacitor plate comprises a silicided, doped polysilicon layer formed on said STI region.

40. A method in accordance with claim 39 wherein said first capacitor HiK dielectric layer consists of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃.

23-1. A method in accordance with claim 22 wherein said first capacitor HiK dielectric layer consists of a material selected from the group consisting of Ta₂O₅, BaTiO₃, HfO₂, ZrO₂, and Al₂O₃.