SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME

• US 20090010080A1
• Filed: 08/29/2008
• Published: 01/08/2009
• Est. Priority Date: 11/09/1999
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Fujioka, Shinya, Sato, Kotoku, Nishimura, Koichi, Kawakubo, Tomohiro
• Granted Patent: US 7,903,487 B2
• Time in Patent Office: Days
• US Class Current: 365/189.90
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3234 Power saving characterised by the action undertaken
• CPC Class Codes: G06F 1/3268 Power saving in hard disk drive
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 2211/4067 Refresh in standby or low power modes
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Claims

1-6. -6. (canceled)

7. A semiconductor device comprising:

a memory core that includes a sense amplifier which receives an internal voltage from an internal power supply line and a dynamic memory cell;

a command decoder that receives a plurality of control signals and generates an internal command signal; and

an internal voltage generator that generates the internal voltage based on an external voltage and supplies the internal voltage to the internal power supply line;

wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in a low power consumption mode where a refresh operation is prohibited.

17. A semiconductor device comprising:

a memory core that includes a sense amplifier which receives an internal voltage from a internal power supply line and a dynamic memory cell;

a command decoder that receives a plurality of control signals and generates an internal command signal;

an internal voltage generator that generates the internal voltage based on an external voltage and supplies the internal voltage to the internal power supply line; and

a low power entry circuit that receives at least one of the plurality of control signals and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited,

wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in response to the low power signal.

27. A semiconductor device comprising:

a memory core that includes a sense amplifier which receives an internal voltage from an internal power supply line and a dynamic memory cell; and

an internal voltage generator that generates the internal voltage based on an external voltage and supplies the internal voltage to the internal power supply line;

wherein the internal voltage generator stops supplying the internal voltage to the internal power supply line in a low power consumption mode where a refresh operation is prohibited.

37. A semiconductor device comprising:

a memory core that includes a sense amplifier which received an internal voltage from an internal power supply line and a dynamic memory cell;

a command decoder that received a plurality of control signals and generates an internal command signal; and

an internal voltage generator that generates the internal voltage based on an external voltage and supplies the internal voltage to the internal power supply line;

wherein the internal voltage generator is inactivated in a low power consumption mode where a refresh operation is prohibited.

48. A semiconductor device comprising:

a memory core that includes a sense amplifier which receives an internal voltage from an internal power supply line and a dynamic memory cell;

a command decoder that receives a plurality of control signals and generates an internal command signal; and

an internal voltage generator that includes a plurality of generator circuits and generates the internal voltage based on an external voltage and supplies the internal voltage to the internal power supply line;

wherein at least one of generator circuits is inactivated in a low power consumption mode where a refresh operation is prohibited.

59. A semiconductor device comprising:

a memory core that operates with a first internal voltage in an operation mode and includes a sense amplifier which receives an internal voltage form an internal power supply line and a dynamic memory cell; and

a command decoder that received a plurality of control signals and generates an internal command signal,

wherein the sense amplifier includes pair transistors, sources of which are coupled to the internal power supply line,

wherein the internal power supply line is supplied a second internal voltage, which is lower than the first internal voltage, in a low power consumption mode where a refresh operation is prohibited.