DISTRIBUTED INTERCONNECT BUS APPARATUS

• US 20090024782A1
• Filed: 01/28/2008
• Published: 01/22/2009
• Est. Priority Date: 07/19/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Wilocity, Ltd. (Qualcomm, Inc.)
• Inventors: Elboim, Yaron
• Granted Patent: US 9,075,926 B2
• Time in Patent Office: Days
• US Class Current: 710/313
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 2213/0026 PCI express

Abstract

A distributed interconnect bus apparatus for connecting peripheral devices. The apparatus can be utilized to wirelessly connect peripheral devices or to allow the connectivity of such devices over a network. The apparatus includes a first bridge coupled to a root component of an interconnect bus; and a second bridge coupled to an endpoint component of an interconnect bus. The apparatus may further include an acknowledgment (ACK) termination for generating at least an ACK signal; and a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.

Claims

1. A distributed interconnect bus apparatus enabling the distributed connection of peripheral devices, comprising:

a first bridge coupled to a root component of an interconnect bus; and

a second bridge coupled to an endpoint component of an interconnect bus.

2. The apparatus of claim 1, wherein the first bridge comprises:

an acknowledgment (ACK) termination for generating at least an ACK signal; and

a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.

3. The apparatus of claim 2, wherein the ACK termination generates the ACK signal upon reception of a data packet sent from either the root component or the second bridge.

4. The apparatus of claim 3, wherein the flow control mechanism saves data packets sent either from the root component or the second bridge.

5. The apparatus of claim 1, wherein the second bridge comprises:

an ACK termination for generating at least an ACK signal; and

a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.

6. The apparatus of claim 5, wherein the ACK termination generates the ACK signal upon reception of a data packet sent either from the endpoint component or the first bridge.

7. The apparatus of claim 6, wherein the flow control mechanism saves data packets sent either from the endpoint component or the first bridge.

8. The apparatus of claim 1, wherein the interconnect bus is at least a PCI Express (PCIe) bus.

9. The apparatus of claim 8, wherein the root component comprises at least one of:

a PCIe root and a PCIe switch.

10. The apparatus of claim 8, wherein the endpoint component comprises at least a PCIe endpoint.

11. The apparatus of claim 1, wherein the interconnect bus further comprises at least one of:

a universal serial bus (USB), a PCIe second generation bus, a PCIe third generation bus, a Hypertransport bus, and an Infiniband bus.

12. A distributed interconnect bus apparatus enabling the distributed connection of peripheral devices over a wireless medium, comprising:

a first bridge coupled to a root component of an interconnect bus;

a first wireless transceiver coupled to the first bridge;

a second bridge coupled to a endpoint component of an interconnect bus; and

a second wireless transceiver coupled to the second bridge.

13. The apparatus of claim 12, wherein the first bridge comprises:

an acknowledgment (ACK) termination for generating at least an ACK signal; and

a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.

14. The apparatus of claim 12, wherein the second bridge comprises:

an ACK termination for generating at least an ACK signal; and

a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.

15. The apparatus of claim 12, wherein the wireless first transceiver and the wireless second transceiver implement a wireless modem.

16. The apparatus of claim 12, wherein the interconnect bus comprises at least a PCI Express (PCIe) bus.

17. The apparatus of claim 16, wherein the root component comprises at least one of:

a PCIe root, a PCIe switch, and a PCIe endpoint.

18. The apparatus of claim 16, wherein the endpoint component comprises at least one of:

a PCIe root, a PCIe switch, and a PCIe endpoint.

19. The apparatus of claim 12, wherein the interconnect bus further comprises at least one of:

a universal serial bus (USB), a PCIe second generation bus, a PCIe third generation bus, a Hypertransport bus, and an Infiniband bus.

20. A distributed interconnect bus apparatus enabling the distributed connection of peripheral devices over a network, comprising:

a first bridge coupled to a root component of an interconnect bus;

a first network adapter coupled to the first bridge;

a second bridge coupled to a endpoint component of the interconnect bus; and

a second network adapter coupled to the second bridge.

21. The apparatus of claim 20, wherein the first bridge comprises:

an acknowledgment (ACK) termination for generating at least an ACK signal; and

a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.

22. The apparatus of claim 20, wherein the second bridge comprises:

an ACK termination for generating at least an ACK signal; and

a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions.

23. The apparatus of claim 20, wherein the network includes at least one of:

a personal area network (PAN) a local area network (LAN), a wide area network (WAN), and a metropolitan area network (MAN).

24. The apparatus of claim 20, wherein the interconnect bus comprises at least a PCI Express (PCIe) bus.

25. The apparatus of claim 20, wherein the root component comprises at least one of:

a PCIe root, a PCIe switch, and a PCIe endpoint.

26. The apparatus of claim 20, wherein the endpoint component comprises at least one of:

a PCIe root, a PCIe switch, and a PCIe endpoint.

27. The apparatus of claim 20, wherein the interconnect bus further comprises at least one of:

a universal serial bus (USB), a PCIe second generation bus, a PCIe third generation bus, a Hypertransport bus, and an Infiniband bus.