NOR-type channel-program channel-erase contactless flash memory on SOI

• US 20090029511A1
• Filed: 08/01/2005
• Published: 01/29/2009
• Est. Priority Date: 02/18/2004
• Status: Abandoned Application

• Current Assignee: Koucheng Wu
• Original Assignee: Koucheng Wu
• Inventors: Wu, Koucheng
• Application Number:
  US11/193,652
• Publication Number:
  US 20090029511A1
• Time in Patent Office: Days
• US Class Current: 438/261
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device having an electrically erasable programmable read only memory (EEPROM) comprises a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer. Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region. The semiconductor device further comprises a plurality of gate lines each connecting the gate regions of a row of EEPROM memory cells, a plurality of body lines each connecting the body regions of a column of EEPROM memory cells, a plurality of source lines each connecting the source regions of a column of EEPROM memory cells, and a plurality of drain lines each connecting the drain regions of a column of EEPROM memory cells. The source lines and the drain lines are buried lines, and the source regions and the drain regions of a column of EEPROM memory cells are insulated from the source regions and the drain regions of the adjacent columns of EEPROM memory cells.

Claims

1. A method of manufacturing a semiconductor device having an electrically erasable programmable read only memory (EEPROM) having a plurality of EEPROM cells, comprising:

providing a silicon-on-insulator (SOI) wafer comprising a top silicon layer of a first conductivity type;

growing a gate insulation film over the top silicon layer;

depositing a floating-gate layer over the gate insulator;

patterning the floating-gate layer and the gate insulation film in a first photo-masking step to form floating-gate structures in column-wise stripes;

implanting impurities on the top silicon layer to form heavily doped areas of a second conductivity type, wherein the heavily doped areas are self-aligned to the floating-gate structures;

forming insulating floating-gate sidewall spacers on the side walls of the column-wise floating-gate structures;

removing the heavily doped area in the exposed top silicon layer between the insulating floating-gate sidewall spacers by etching to form electrically isolated heavily doped areas and grooves between the electrically isolated heavily doped areas, wherein the grooves and the electrically isolated heavily doped areas are self-aligned to the floating-gate structures;

forming a first insulation film over the grooves between the two heavily doped regions, wherein the first insulation film is in stripe-wise pattern and self-aligned to the floating-gate structure;

forming an inter-gate dielectric layer over the wafer;

depositing a control gate layer over the wafer;

patterning the control gate layer to form row-wise control-gate stripes in a second photo-masking step; and

removing the floating-gate structures not covered by the control-gate stripes by etching such that the remaining floating-gate structures are self-aligned to the control-gate stripes.

2. A method of claim 1, wherein the EEPROM cells comprise source regions and drain regions formed in the electrically isolated heavily doped areas in the top silicon layer.

3. A method of claim 1, further comprising

depositing a first sacrificial insulating film over the floating-gate layer after the floating-gate layer is deposited over the gate insulator;

patterning the first sacrificial insulating film in the first photo-masking step such that the floating-gate structures further include the first sacrificial insulating film; and

removing the sacrificial insulating film before an inter-gate dielectric layer is formed over the wafer.

4. A method of claim 1, further comprising

forming conductive floating-gate sidewall spacers on the side walls of said column-wise floating-gate structures before an inter-gate dielectric layer is formed over the wafer, wherein the floating-gate sidewall spacers are electrically connected with the floating-gate layer and the floating-gate sidewall spacers are self-aligned to the floating-gate structures.

5. A method of manufacturing a semiconductor device having an electrically erasable programmable read only memory (EEPROM) having a plurality of EEPROM cells, comprising:

providing a silicon-on-insulator (SOI) wafer comprising a top silicon layer of a first conductivity type;

growing a first insulation film over the top silicon layer;

forming a charge storage layer over the first insulation film;

growing a second insulation film over the charge storage layer;

depositing a column-gate layer over the second insulation film;

patterning the column-gate layer in a first photo-masking step to form column gates in column-wise stripes;

implanting impurities on the top silicon layer to form heavily doped areas of a second conductivity type, wherein the heavily doped areas are self-aligned to the column gates;

forming insulating sidewall spacers on the side walls of the column gates;

removing the heavily doped area in the exposed top silicon layer between the insulating sidewall spacers by etching to form electrically isolated heavily doped areas and grooves between the electrically isolated heavily doped areas, wherein the grooves and the electrically isolated heavily doped areas are self-aligned to the column gates;

forming an insulation film over the grooves, wherein the insulation film is in stripe-wise pattern and self-aligned to the column gates;

depositing a control gate layer over the wafer; and

patterning the control gate layer to form row-wise control-gate stripes in a second photo-masking step.

6. A method of claim 5, wherein the EEPROM cells comprise source regions and drain regions formed in the electrically isolated heavily doped areas in the top silicon layer.

7. A method of claim 5, wherein the charge storage layer is made of silicon nitride, Al₂O₃, or AlN.

8. A method of claim 5, wherein the charge storage layer consists of mutually isolated silicon or germanium nanocrystals.

9. A method of claim 5, wherein the column-gate layer is made of polysilicon.

10. A method of claim 5, further comprising

removing the column-gate layer not covered by the control-gate stripes by etching such that the remaining column gates are self-aligned to the control-gate stripes.

11. A method of claim 5, further comprising

removing the column-gate layer by etching before depositing the control gate layer.