METHOD OF DIGITAL EXTRACTION FOR ACCURATE FAILURE DIAGNOSIS

• US 20090033335A1
• Filed: 01/03/2008
• Published: 02/05/2009
• Est. Priority Date: 07/30/2007
• Status: Active Grant

• Current Assignee: Carl Z. Zhou
• Original Assignee: Carl Z. Zhou
• Inventors: Vohra, Fazela M., Zhou, Carl Z.
• Granted Patent: US 7,945,417 B2
• Time in Patent Office: Days
• US Class Current: 324/537
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability

Abstract

A method for testing VLSI circuits comprises a two-pass diagnostic method for testing a circuit wherein a first pass comprises a conventional test flow wherein an ATPG tool generates a set of test patterns and identifies possible faulty nets within the circuit. A second pass focuses on a designated critical subset of the circuit extracted using a method for extracting a subset for failure diagnosis of the tested circuit. A second pass utilizes an extraction algorithm which extracts one or more critical subsets of the circuit in order to obtain more accurate failure diagnosis.

Claims

1. A method for testing VLSI circuits comprising the steps of:

generating a set of test patterns for an original circuit;

running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit;

providing an extraction algorithm;

extracting a subset of the original circuit for failure diagnosis utilizing the provided extraction algorithm;

the extracting step further comprising the step of eliminating unnecessary circuit elements from the original circuit; and

testing the extracted subset to diagnose reasons for failure of the identified faulty nets.

2. A method for testing VLSI circuits comprising the steps of:

generating a set of test patterns for an original circuit;

running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit;

providing an extraction algorithm comprising a series of rules for eliminating unnecessary circuit elements from the original circuit;

executing the rules of the extraction algorithm and thereby extracting a subset of the original circuit for failure diagnosis; and

testing the extracted subset and thereby identifying a reduced number of faulty nets; and

thereafter diagnosing root causes for failure of the original circuit.

3. A method for extracting a critical subset circuit from an original circuit for performing failure diagnosis on identified faulty nets within the circuit comprising the steps of:

providing an original circuit;

providing an extraction algorithm comprising a series of rules for eliminating unnecessary circuit elements from the original circuit;

defining a subset circuit within the original circuit containing all faulty nets and surrounding circuitry traced up to primary and pseudo primary inputs;

extracting a reduced circuit from the defined subset;

the reduced circuit comprising at least one complete path from one faulty site of one faulty net to the primary and pseudo primary inputs; and

passing the reduced circuit through a pattern generation test tool for fault diagnosis of the one faulty net within the reduced circuit.

4. The method for extracting a critical subset circuit from an original circuit for performing failure diagnosis of the original circuit comprising claim 3 further characterized by the steps of:

generating a set of test patterns for the original circuit;

running a test on the original circuit utilizing the generated test patterns;

providing a list of faulty nets identified during the test on the original circuit;

defining critical paths for each identified faulty net such that at each identified net comprises at least one unique complete path from the identified net to primary or pseudo primary inputs of the original circuit and at least one unique complete path to primary or pseudo primary outputs of the original circuit;

assigning net values for all nets surrounding the identified nets;

assigning net values for critical paths of the identified nets and surrounding critical paths; and

eliminating nets and paths not associated with the identified nets.

5. A method for extracting a critical subset circuit from an original circuit for performing failure diagnosis on interested faulty nets within the circuit identified during previous testing operations comprising the steps of:

defining critical paths for each identified net such that at each identified net comprises at least one unique complete path from the identified net to primary or pseudo primary inputs of the original circuit and at least one unique complete path to primary or pseudo primary outputs of the original circuit;

assigning net values for all nets surrounding the identified nets;

assigning net values for critical paths of the identified nets and surrounding critical paths; and

eliminating nets and paths not associated with the identified nets.

6. A method for testing VLSI circuits comprising hie steps of:

generating a set of test patterns for an original circuit;

running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit;

providing an extraction algorithm comprising the steps of;

a) providing a synthesized, full scan netlist of the original circuit;

b) providing a possible candidate fault list which contains each existing fault within the circuit, each existing fault having a gate name and position;

c) assigning net types to all nets within the original circuit, the net types selected from the group consisting of Core (C), extended (E), to be decided (D), can be passivated (P), and can be ignored (X);

d) assigning net attributes for all type P and D nets;

e) converting assigned type P and D nets to either type E or X nets;

t) re-assigning net attributes to converted nets; and

g) repeating steps e and i until all type D nets are converted to either type E or X nets and all P nets have net possibility attributes of “

Y;

”

extracting a reduced circuit from the defined subset according to the provided extraction algorithm, the reduced circuit comprising at least one complete path from one faulty site of one faulty net to the primary and pseudo primary inputs; and

passing the reduced circuit through a pattern generation test tool for fault diagnosis of the one faulty net within the reduced circuit.

7. A method for testing VLSI circuits according to claim 6 wherein the net types are assigned to all nets within the original circuit according to a method comprising the steps of:

a) assigning net type C to all interested nets;

b) assigning net type E to any unassigned nets that are the output nets of gates whose input nets contain C or E nets;

c) assigning net type D to any unassigned nets that are multiple output nets of a stem whose input net is C or E net;

d) assigning net type D to any unassigned nets for which the net'"'"'s upstream nets contain D nets;

e) assigning net type E to any unassigned net that is the sole input of a stem or a gate whose outputs contain C or E nets;

f) assigning net type P to any unassigned nets that are input nets of gates whose outputs are C, E, or D nets;

g) assigning net type P to any unassigned nets whose downstream nets contain P nets; and

h) assigning net type X to any remaining unassigned nets.

8. A method for testing VLSI circuits according to claim 6 wherein the net attributes are assigned to all type P nets according to a method comprising the steps of:

a) Assigning source attribute ‘

E’

to any P nets which are inputs of gates whose outputs are either C or E nets;

b) Assigning source attribute ‘

D’

to any P nets which are inputs of gates whose outputs are D nets;

c) Assigning source attribute ‘

E’

to any P nets with downstream P nets having source attribute ‘

E’

;

d) Assigning source attribute ‘

D’

to any P nets with downstream P nets having source attribute ‘

D’

;

e) Assigning value attribute ‘

1’

to P nets which are inputs of AND or NAND gates whose outputs are C, E, or D nets;

f) Assigning value attribute ‘

0’

to P nets which are inputs of OR or NOR gates whose outputs are (C, E, or D nets;

g) For P nets that are inputs of gates whose outputs are P nets, assigning value attributes so that when the input P nets'"'"' logic states are set as the input P net value attributes, the output P nets are at the logic states as indicated by the output P net value attributes;

h) For any P net that is an input of a stem, assigning the same value attribute as that of the output P nets if all output P nets have the same value attribute;

if output P nets have different value attributes, assign the stem input P net value attribute ‘

0&

1’

;

i) Assigning value attribute ‘

0&

1’

to any P nets with downstream P net value attributes of ‘

0&

1’

;

j) Assigning possibility attribute ‘

N’

to P nets which are stem outputs and the corresponding stem inputs are E nets;

k) Assigning possibility attribute ‘

CE’

to any P net which (1) is an output of a stem whose input P net has a value attribute of ‘

0&

1’ and

(2) at least one of the stem output P nets with source attribute ‘

E’

has a value attribute different from its own value attribute;

l) Assigning possibility attribute ‘

CD’

to any P net which (1) is an outputs of a stem whose input P nets have value attribute ‘

0&

1’ and

(2) all stem output P nets that have different value attributes have source attribute ‘

D’

;

m) Assigning possibility attribute ‘

N’

to P nets with upstream P nets having possibility attribute ‘

N’

;

n) Assigning possibility attribute ‘

CE’

to P nets with upstream P nets having possibility attribute ‘

CE’ and

with possibility attributes which have not been assigned in any of the previous steps (i) through (xii);

o) Assigning possibility attribute ‘

CD’

to P nets with upstream P nets having possibility attribute ‘

CD’ and

with possibility attributes which have not been assigned in any of the previous steps (i) through (xiv);

p) Assigning possibility attribute ‘

C’

to P nets having a value attribute of ‘

0&

1’ and

with possibility attributes which have not been assigned in any of the previous steps (a) through (o);

q) Assigning possibility attribute ‘

Y’

to any P nets whose possibility attributes have not been assigned in any of the previous steps (a) through (p).

9. A method for testing VLSI circuits according to claim 6 wherein the net attributes are assigned to all type D nets according to a method comprising the steps of:

a) Assigning difficulty attribute ‘

0’

to any D nets having paths which can reach primary or pseudo primary outputs without intersecting any other C/E/D net paths at gates and if all passivating P nets, if any, along the paths have possibility attribute “

Y”

;

b) Assigning difficulty attribute ‘

1’

to any D nets having paths which can reach primary or pseudo primary outputs without intersecting any other C/E/D paths at gates and at least one of said D net'"'"'s passivated P nets has possibility attribute ‘

CD’

but none having possibility attribute ‘

CE’

;

c) Assign difficulty attribute ‘

2’

to any D nets having paths which can reach primary or pseudo primary outputs without intersecting any C/E/D paths at gates and at least one of said D net'"'"'s passivated P nets has possibility attribute ‘

CE’

;

d) Assigning difficulty attribute ‘

3’

to any D nets having paths which can reach primary or pseudo primary outputs without intersecting any C/E/D paths at gates and at least one of said D net'"'"'s passivated P nets has possibility attribute ‘

N’

;

e) Assigning difficulty attribute ‘

4’

to any D nets having paths which intersect with other D net paths at gates, but do not intersect with C or E nets at gates; and

f) Assigning difficulty attribute ‘

5’

to any D nets having paths which intersect with other C or E net paths at gates.

10. A method for testing VLSI circuits according to claim 6 wherein the nets are converted into a different net type according to a method comprising the steps of:

a) Converting D nets with difficulty attribute of ‘

5’

into E nets;

b) Re-assigning net attributes according to a method for assigning net attributes;

c) Repeating steps a) and b) until there are no remaining D nets with difficulty attribute of ‘

5’

;

d) Converting any stein at which the input is a C or E net and some outputs are D nets, among which there is at least one D net path with difficulty attribute ‘

0’

according to a first conversion procedure comprising the steps of;

i. Converting the D net path that least intersects with P nets among the paths of D nets having a difficulty attribute of ‘

0’

into E net path;

ii. Converting all D net paths at the stem output with a difficulty attribute of ‘

4’

into P nets; and

iii. Converting all other remaining D net paths at the stem output along with said D nets'"'"' passivated P net paths into X net paths;

e) Re-assigning net attributes as described in the procedures for assigning net attributes;

f) Repeating steps d) and e) until there are no remaining D net paths with a difficulty attribute of ‘

0’

;

g) Converting any stem at which the stem'"'"'s input is a C or E net and some outputs are D nets among which at least one D net path has difficulty attribute value of ‘

1’

according to a second conversion procedure comprising the steps of;

i. Convert the D net path that least intersects with P nets among the difficulty attribute ‘

1’

D net paths into an E net path;

ii. Convert all D net paths at the stem output with a difficulty attribute of ‘

4’

into P nets;

iii. Convert all other D net paths at the stern output along with said D nets'"'"' passivated P net paths into X net paths;

h) Re-assigning net attributes as described in the procedures for assigning net attributes;

i) Repeating steps d) through h) until all D net paths have difficulty attributes larger than 1;

j) Converting any stem at which the stem'"'"'s input is a C or E net and some outputs are D nets among which there are at least one D net path with a difficulty attribute of ‘

2’

according to a third conversion procedure comprising the steps;

i. Converting the D net path that least intersects with P nets among the paths of D nets having a difficulty attribute of ‘

2’

into an E net path;

ii, Converting all D net paths at the stem output having a difficulty attribute of ‘

4’

into P nets; and

iii. Convert all other D net paths at the stem output along with said D nets'"'"' passivated P net paths into X net paths;

k) Reassigning net attributes as described in the procedures for assigning net attributes;

l) Repeating steps d) through k) until all D net paths have difficulty attributes larger than 2;

m) Converting any stem at which the input is a C or E net and some outputs are D nets among which at least one D net path has a difficulty attribute value of ‘

3’

according to a fourth conversion procedure comprising the steps of;

i. Converting the D net path that least intersects with P nets among the paths of D nets having difficulty attribute ‘

3’

into an E net path;

ii. Converting all difficulty attribute ‘

4’

D net paths at the stem output into P net paths; and

iii. Converting all other remaining D net paths at the stem output along with said D nets'"'"' passivated P net paths into X net paths;

n) Re-assigning net attributes as described in the procedures of assigning net attributes;

o) Repeating steps d) through n) until all D net paths have difficulty attributes larger than 3;

p) Converting all D nets into E nets;

q) Re-assigning net attributes as described in the procedures for assigning net attributes;

r) Converting any gate at which all inputs are P nets and the output is C or E net, if there is at least one input P net having possibility attribute ‘

Y’

, choose the P net path that intersects the least number of other P net paths among the possibility attribute ‘

Y’

P net paths into an E net path;

s) Re-assigning net attributes as described in the procedures for assigning net attributes;

t) Converting all P nets that have possibility attribute other than ‘

Y’

into E nets.

11. A method for fault diagnosing in VLSI circuits comprising the steps of:

a) generating a set of test patterns for an original circuit;

b) running a test on the original circuit utilizing the generated test patterns and identifying faulty nets within the circuit;

c) providing an extraction algorithm;

d) extracting a subset of the original circuit for failure diagnosis utilizing the provided extraction algorithm, wherein the extracted subset eliminates unnecessary circuit elements from the original circuit;

e) generating test patterns for the extracted subset;

f) mapping test patterns generated for the extracted subset back to the original circuit;

g) testing the original circuit utilizing the test patterns generated for the extracted subset to diagnose reasons for failure of the identified faulty nets;

h) generating a new set of interested nets from test results from the test utilizing the test patterns generated for the extracted subset; and

i) repeating steps d through h until a smallest desired diagnostic resolution is reached.