Methods and apparatuses for supplying current using a digital sequence

• US 20090040326A1
• Filed: 08/09/2007
• Published: 02/12/2009
• Est. Priority Date: 08/09/2007
• Status: Abandoned Application

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Lee, Chiajen Michael, Miao, Tien-Min
• Application Number:
  US11/889,172
• Publication Number:
  US 20090040326A1
• Time in Patent Office: Days
• US Class Current: 348/222.100
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H04N 23/651 for reducing power consumption by affecting camera operations, e.g. sleep mode, hibernation mode or power off of selective parts of the camera
• CPC Class Codes: H04N 23/667 Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes

Abstract

Methods and apparatuses for supplying current to an electronic device include incrementally changing an output current supplied to the device according to a digital sequence.

Claims

1. A method of supplying current to an electronic device comprising:

receiving an input current; and

incrementally changing an output current supplied to the device according to a digital sequence based on the input current.

2. The method of claim 1, wherein the digital sequence comprises at least two bits.

3. The method of claim 1, wherein the digital sequence comprises a linear sequence.

4. The method of claim 1, wherein the digital sequence comprises a nonlinear sequence.

5. The method of claim 1, wherein the digital sequence comprises a Gray code.

6. A method of supplying current to a digital camera comprising:

outputting a current at a first level in a first mode; and

gradually increasing or decreasing the output current from the first current level to a second current level according to a digital sequence, the second current level different from the first current level.

7. The method of claim 6, wherein:

the first mode comprises a camera preview mode.

8. The method of claim 6, wherein the second mode comprises a camera image capture mode.

9. The method of claim 6, wherein the first mode comprises a no-power mode.

10. The method of claim 6, wherein the step of gradually increasing or decreasing the output current comprises conforming the output current level to a predetermined curve.

11. The method of claim 6, wherein:

gradually increasing or decreasing the output current occurs from a first time to a second time later than the first time; and

at the second time a mode signal is asserted, indicating that the electronic device is in the second mode.

12. The method of claim 11, wherein at a third time later than the second time, the mode signal is deasserted.

13. An apparatus for supplying current to an imaging device comprising:

a control circuit configured to output a digital word; and

a plurality of sequence bit transistors, each sequence bit transistor comprising;

a gate configured to receive a respective bit of the digital word;

an input source/drain region configured to receive an input current from a common current supply; and

an output source/drain region configured to output a respective bit output current,

wherein the control circuit outputs the digital word in a sequence of steps to output one or more bit output currents to gradually change a total output current from a first mode current level to a second mode current level.

14. The apparatus of claim 13, further comprising a plurality of output biasing transistors, each output biasing transistor comprising:

an output source/drain region respectively coupled to the input source/drain region of each of the plurality of sequence bit transistors; and

a gate configured to receive a biasing input voltage.

15. The apparatus of claim 13, wherein the first mode comprises a camera preview mode.

16. The apparatus of claim 13, wherein the second mode comprises a camera image capture mode.

17. The apparatus of claim 13, wherein the first mode comprises a no-power mode.

18. A camera system comprising:

a lens;

a pixel array and readout circuit for capturing image data;

a processing circuit configured to output a digital control word;

a plurality of sequence bit transistors, each sequence bit transistor comprising;

a gate configured to receive a respective bit of the digital control word;

an input source/drain region configured to receive an input current from a common current supply; and

an output source/drain region configured to output a respective bit output current; and

a current output terminal for outputting a supplied current based on the bit output currents from the plurality of sequence bit transistors,

wherein the processing circuit outputs the digital control word to progress through a predetermined sequence of digital codes to incrementally adjust the supplied current through the current output terminal.

19. The camera system of claim 18, further comprising a plurality of output biasing transistors, each output biasing transistor comprising:

an output source/drain region respectively coupled to the input source/drain region of each of the plurality of sequence bit transistors; and

a gate configured to receive a biasing input voltage.