Method and apparatus providing shared pixel straight gate architecture

• US 20090046189A1
• Filed: 08/17/2007
• Published: 02/19/2009
• Est. Priority Date: 08/17/2007
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Yin, Zhiping, Fan, Xiaofeng
• Granted Patent: US 7,924,333 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14641 Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

Methods and apparatuses using four-way-shared readout circuits to increase pixel fill factor.

Claims

1. A pixel array comprising:

a plurality of pixel blocks organized into rows and columns, each block comprising;

first, second, third, and fourth pixels, each pixel having a respective photosensor for generating photocharges;

a common storage node shared by the first, second, third, and fourth pixels and for storing the generated photocharges;

a shared readout circuit connected to said common storage node; and

first, second, third, and fourth rectilinear transfer gates for selectively transferring photocharges from an associated pixel to the common storage node;

wherein each of the transfer gates overlaps an edge of the photosensor in its associated pixel.

2. The pixel array of claim 1, wherein each of the transfer gates is oriented parallel to the edge it overlaps.

3. The pixel array of claim 1 further comprising a reset transistor for resetting the charges stored at the common storage node.

4. The pixel array of claim 1, wherein the shared readout circuit includes at least one of a common source follower transistor having a gate connected to said common storage node and a common row select transistor for gating the output of said source follower transistor.

5. The pixel array of claim 1, wherein two of the first, second, third and fourth pixels are two adjacent pixels in a row of the array.

6. The pixel array of claim 4, wherein two of the first, second, third and fourth pixels are adjacent pixels in a column of the array.

7. The pixel array of claim 1, wherein the shared readout circuit is located in an active region located between a first and second pair of photosensors.

8. The pixel array of claim 1, wherein the first transfer gate is further connected to a photosensor outside the pixel block and transfers photocharge from the photosensor outside the pixel block to a second common storage node.

9. An imager comprising:

a plurality of pixel blocks organized into rows and columns, each block comprising;

first, second, third, and fourth photosensors for generating photocharges in response to light;

a common storage node shared by the first, second, third, and fourth photosensors;

first, second, third, and fourth transfer gates for transferring photocharges to the common storage node from a respective one of the first, second, third, and fourth photosensors;

a common reset transistor for resetting the charge at the common storage node; and

a readout circuit comprising at least one common transistor for producing at least one signal representing an amount of charge stored at the common storage node, at least a portion of the readout circuit being located in an active region between the first, second, third, and fourth photosensors;

wherein each of the transfer gates overlaps an edge of its first associated pixel and an edge of a second associated pixel.

10. The imager of claim 9, wherein the second associated pixel is in the same column as the first associated pixel.

11. The imager of claim 9, wherein the first, second, third or fourth photosensors each comprise a photodiode.

12. An imaging system comprising:

a pixel array comprising;

a plurality of pixel blocks organized into rows and columns, each block comprising;

first, second, third, and fourth pixels, each pixel having a respective photosensor for generating photocharges;

a common storage node shared by the first, second, third, and fourth pixels and for storing the generated photocharges;

a shared readout circuit connected to said common storage node; and

first, second, third, and fourth transfer gates for transferring photocharges to the common storage node from a respective one of the first, second, third, and fourth photosensors;

wherein each photosensor is connected to a ground contact;

wherein each of the transfer gates overlaps an entire edge of the photosensor in its associated pixel and the common storage node; and

wherein each of the transfer gates overlaps a photosensor in an adjacent pixel block and a second common storage node in the second pixel block.

13. The imaging system of claim 12, wherein each photosensor is a PNP-type photodiode, and the N-region of each photodiode is electrically grounded.

14. The imaging system of claim 12, wherein the imaging system comprises a digital still camera.

15. The imaging system of claim 12, wherein the imaging system comprises a digital single-lens reflex camera.

16. The imaging system of claim 12, wherein the imaging system comprises a digital video camera.

17. A method of fabricating an integrated circuit, comprising:

forming an array of pixels arranged in a plurality of rows and a plurality of columns on a substrate,

forming a plurality of charge storage nodes on the substrate,

forming a plurality of transfer gates on the substrate,

wherein each transfer gate is oriented such that its length is parallel to a column of pixels, and

wherein each transfer gate overlaps the edges of at least two pixels in a column and overlaps at least two charge storage nodes.