E-BEAM INSPECTION STRUCTURE FOR LEAKAGE ANALYSIS

• US 20090057664A1
• Filed: 08/28/2007
• Published: 03/05/2009
• Est. Priority Date: 08/28/2007
• Status: Active Grant

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: LAM, Jeffrey, LIM, Victor Seng Keong
• Granted Patent: US 7,939,348 B2
• Time in Patent Office: Days
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined structural defect. The eight test structures being: 1) having an Active Area (AA)/P-N junction leakage; 2) having an isolation region to ground; 3) having an AA/P-N junction and isolation region; 4) having a gate dielectric leakage and gate to isolation region to ground; 5) having a gate dielectric leakage through AA/P-N junction to ground leakage; 6) having a gate dielectric to ground and gate/ one side isolation region leakage to ground; 7) having an oversized gate dielectric through AA/P-N junction to ground leakage; and 8) having an AA/P-N junction leakage gate dielectric leakage.

Claims

1. A testing structure comprised of at least two different test structures, each of the at least two different test structures exhibit a discernable defect characteristic upon voltage contrast (VC) scanning when any test structure that exhibits the discernable defect characteristic has at least one predetermined structural defect.

2. The testing structure of claim 1 wherein the at least two different test structures further comprise specific structures designed to permit an observer of any said discernable defect characteristic to exclude one or more possible said structural defects.

3. The testing structure of claim 1 wherein the at least two different test structures are selected from the following structures:

1) a first test structure having an Active Area (AA)/P-N junction leakage test structure;

2) a second test structure having an isolation region to ground test structure;

3) a third test structure having an AA/P-N junction and isolation region test structure;

4) a fourth test structure having a gate dielectric leakage and gate to isolation region to ground test structure;

5) a fifth test structure having a gate dielectric leakage through AA/P-N junction to ground leakage test structure;

6) a sixth test structure having a gate dielectric to ground and gate/one side isolation region leakage to ground test structure;

7) a seventh test structure having an oversized gate dielectric through AA/P-N junction to ground leakage test structure;

or

8) an eighth test structure having an AA/P-N junction leakage gate dielectric leakage test structure.

4. A testing structure comprised of at least one test structure, the at least one test structure exhibits a discernable defect characteristic upon voltage contrast (VC) scanning when any test structure that exhibits the discernable defect characteristic has at least one predetermined structural defect;

the at least one test structure is selected from the following first through eighth test structures;

1) a first test structure having an Active Area (AA)/P-N junction leakage test structure;

2) a second test structure having an isolation region to ground test structure;

3) a third test structure having an AA/P-N junction and isolation region test structure;

4) a fourth test structure having a gate dielectric leakage and gate to isolation region to ground test structure;

5) a fifth test structure having a gate dielectric leakage through AA/P-N junction to ground leakage test structure;

6) a sixth test structure having a gate dielectric to ground and gate/one side isolation region leakage to ground test structure;

7) a seventh test structure having an oversized gate dielectric through AA/P-N junction to ground leakage test structure; and

8) an eighth test structure having an AA/P-N junction leakage gate dielectric leakage test structure.

5. The testing structure of claim 4 includes a test site which is comprised of at least two different test structures selected from the first through eighth test structures.

6. The testing structure of claim 4 wherein:

1) the first test structure is comprised of;

one or more first test devices separated by first isolation regions over a substrate, each of the one or more first test devices comprising;

a first well region in the substrate within a first Active Area, the first well region having a first-type-impurity;

a first doped region over and contacting the first well region, the first doped region having a second-type-impurity; and

a first contact plug over and contacting the first doped region;

2) the second test structure is comprised of;

one or more second test devices over the substrate, each of the one or more second test devices comprising;

a second well region contacting the substrate within a second Active Area, the second well region having the first-type-impurity;

a second doped region over and contacting the second well region, the second doped region having the second-type-impurity, the second well region and the second doped region of each of the one or more second test devices being separated by second isolation regions; and

a second contact plug over and contacting the second isolation regions;

3) the third test structure is comprised of;

one or more third test devices over the substrate, each of the one or more third test devices comprising;

a third well region contacting the substrate within a third Active Area, the third well region having the first-type-impurity;

a third doped region over and contacting the third well region, the third doped region having the second-type-impurity;

the third well region and the third doped region of each of the one or more third test devices being separated by third isolation regions; and

a third contact over and contacting at least a portion of both of the respective third isolation regions and the adjacent third doped region;

4) the fourth test structure is comprised of,

one or more fourth test devices isolated by fourth isolation regions over the substrate, each of the one or more fourth test devices comprising;

a fourth well region contacting the substrate within a fourth Active Area, the fourth well region having the first-type-impurity;

a fourth doped region over and contacting the fourth well region, the fourth doped region having the second-type-impurity;

a fourth gate dielectric over and in contact with the fourth doped region and the fourth isolation regions;

a fourth gate structure over and in contact with the fourth gate dielectric and over adjacent fourth isolation regions; and

a fourth contact over and contacting the fourth gate structure;

5) the fifth test structure is comprised of;

one or more fifth test devices separated by fifth isolation regions over the substrate, each of the one or more fifth test devices comprising;

a fifth well region contacting the substrate within a fifth Active Area, the fifth well region having the first-type-impurity;

a fifth doped region over and contacting the fifth well region, the fifth doped region having the second-type-impurity;

a fifth gate dielectric over and in contact with the fifth doped region and not over the fifth isolation regions;

a fifth gate structure over and in contact with the fifth gate dielectric and not over the fifth isolation regions; and

a fifth contact over and contacting the fifth gate structure;

6) the sixth test structure is comprised of;

one or more sixth test devices over the substrate, each of the one or more sixth test devices comprising;

a sixth well region contacting the substrate within a sixth Active Area, the sixth well region having the first-type-impurity;

a sixth doped region over and contacting the sixth well region, the sixth doped region having the second-type-impurity, the sixth well region and the sixth doped region of each of the one or more sixth test devices being separated by sixth isolation regions;

a sixth gate dielectric over and contacting at least a portion of both the sixth doped region and the adjacent sixth isolation region;

a sixth gate structure over and in contact with the sixth gate dielectric and over the adjacent sixth isolation region; and

a sixth contact over and contacting the sixth gate structure;

7) the seventh test structure is comprised of;

one or more seventh test devices separated by seventh isolation regions over the substrate, each of the one or more seventh test devices comprising;

a seventh well region contacting the substrate within a seventh Active Area, the seventh well region having the first-type-impurity;

a seventh doped region over and contacting the seventh well region, the seventh doped region having the second-type-impurity;

a seventh gate dielectric over and in contact with the seventh doped region and not extending to adjacent seventh isolation regions;

a seventh gate structure over and in contact with the seventh gate dielectric; and

a seventh contact over and contacting the seventh gate structure;

wherein a surface area of the seventh doped region is at least about 10% greater than a surface area of the fifth doped region; and

8) the eighth test structure is comprised of;

two or more eighth test devices over the substrate, each of the two or more eighth test devices comprising;

an eighth well region contacting the substrate within an eighth Active Area, the eighth well region having the first-type-impurity;

an eighth doped region over and contacting the eighth well region, the eighth doped region having the second-type-impurity, the eighth well region and the eighth doped region of each of the one or more eighth test devices being separated by eighth isolation regions;

an eighth gate dielectric over and contacting at least a portion of the eighth doped region;

an eighth gate structure over and in contact with the eighth gate dielectric; and

a) at least one of the eighth test devices having an eighth contact over and contacting at least a portion of both the eighth gate structure and the eighth doped region; and

b) at least one of the eighth test devices having an eighth contact over and contacting the eighth doped region but not contacting either the eighth gate dielectric or the eighth gate structure.

7. The testing structure of claim 6 includes a test site which is comprised of at least two different test structures selected from the first through eighth test structures.

8. The testing structure of claim 6 includes a test site which is comprised of at least three or more different test structures selected from the first through eighth test structures.

9. The testing structure of claim 4 wherein at least one of the first through eighth test structures include a first level metal (M1).

10. The testing structure of claim 6 wherein at least one of the first through eighth test structures further comprises a grounding device.

11. The testing structure of claim 6 wherein the first-impurity-type is P-type and the second-impurity-type is N-type.

12. The testing structure of claim 6 wherein the at least one of the first through eighth test structures further comprises a grounding device and a first metal layer.

13. A test method comprised of:

providing at least one test structure over a substrate, the at least one test structure being selected from the following first through eighth test structures;

1) a first test structure having an Active Area (AA)/P-N junction leakage test structure;

2) a second test structure having an isolation region to ground test structure;

3) a third test structure having an AA/P-N junction and isolation region test structure;

4) a fourth test structure having a gate dielectric leakage and gate to isolation region to ground test structure;

5) a fifth test structure having a gate dielectric leakage through AA/P-N junction to ground leakage test structure;

6) a sixth test structure having a gate dielectric to ground and gate/one side isolation region leakage to ground test structure;

7) a seventh test structure having an oversized gate dielectric through AA/P-N junction to ground leakage test structure; and

8) an eighth test structure having an AA/P-N junction leakage gate dielectric leakage test structure; and

scanning the at least one test structure with an electronic beam to detect defects in the at least one test structure.

14. The method of claim 13 wherein:

1) the first test structure is comprised of;

one or more first test devices separated by first isolation regions over the substrate, each of the one or more first test devices comprising;

a first well region in the substrate within a first Active Area, the first well region having a first-type-impurity;

a first doped region over and contacting the first well region, the first doped region having a second-type-impurity; and

a first contact plug over and contacting the first doped region;

2) the second test structure is comprised of;

one or more second test devices over the substrate, each of the one or more second test devices comprising;

a second well region contacting the substrate within a second Active Area, the second well region having the first-type-impurity;

a second doped region over and contacting the second well region, the second doped region having the second-type-impurity, the second well region and the second doped region of each of the one or more second test devices being separated by second isolation regions; and

a second contact plug over and contacting the second isolation regions;

3) the third test structure is comprised of;

one or more third test devices over the substrate, each of the one or more third test devices comprising;

a third well region contacting the substrate within a third Active Area, the third well region having the first-type-impurity;

a third doped region over and contacting the third well region, the third doped region having the second-type-impurity;

the third well region and the third doped region of each of the one or more third test devices being separated by third isolation regions; and

a third contact over and contacting at least a portion of both of the respective third isolation regions and the adjacent third doped region;

4) the fourth test structure is comprised of,

one or more fourth test devices isolated by fourth isolation regions over the substrate, each of the one or more fourth test devices comprising;

a fourth well region contacting the substrate within a fourth Active Area, the fourth well region having the first-type-impurity;

a fourth doped region over and contacting the fourth well region, the fourth doped region having the second-type-impurity;

a fourth gate dielectric over and in contact with the fourth doped region and the fourth isolation regions;

a fourth gate structure over and in contact with the fourth gate dielectric and over adjacent fourth isolation regions; and

a fourth contact over and contacting the fourth gate structure;

5) the fifth test structure is comprised of;

one or more fifth test devices separated by fifth isolation regions over the substrate, each of the one or more fifth test devices comprising;

a fifth well region contacting the substrate within a fifth Active Area, the fifth well region having the first-type-impurity;

a fifth doped region over and contacting the fifth well region, the fifth doped region having the second-type-impurity;

a fifth gate dielectric over and in contact with the fifth doped region and not over the fifth isolation regions;

a fifth gate structure over and in contact with the fifth gate dielectric and not over the fifth isolation regions; and

a fifth contact over and contacting the fifth gate structure;

6) the sixth test structure is comprised of;

one or more sixth test devices over the substrate, each of the one or more sixth test devices comprising;

a sixth well region contacting the substrate within a sixth Active Area, the sixth well region having the first-type-impurity;

a sixth doped region over and contacting the sixth well region, the sixth doped region having the second-type-impurity, the sixth well region and the sixth doped region of each of the one or more sixth test devices being separated by sixth isolation regions;

a sixth gate dielectric over and contacting at least a portion of both the sixth doped region and the adjacent sixth isolation region;

a sixth gate structure over and in contact with the sixth gate dielectric and over the adjacent sixth isolation region; and

a sixth contact over and contacting the sixth gate structure;

7) the seventh test structure is comprised of;

one or more seventh test devices separated by seventh isolation regions over the substrate, each of the one or more seventh test devices comprising;

a seventh well region contacting the substrate within a seventh Active Area, the seventh well region having the first-type-impurity;

a seventh doped region over and contacting the seventh well region, the seventh doped region having the second-type-impurity;

a seventh gate dielectric over and in contact with the seventh doped region and not extending to adjacent seventh isolation regions;

a seventh gate structure over and in contact with the seventh gate dielectric; and

a seventh contact over and contacting the seventh gate structure;

wherein a surface area of the seventh doped region is at least about 10% greater than a surface area of the fifth doped region; and

8) the eighth test structure is comprised of;

two or more eighth test devices over the substrate, each of the two or more eighth test devices comprising;

an eighth well region contacting the substrate within an eighth Active Area, the eighth well region having the first-type-impurity;

an eighth doped region over and contacting the eighth well region, the eighth doped region having the second-type-impurity, the eighth well region and the eighth doped region of each of the one or more eighth test devices being separated by eighth isolation regions;

an eighth gate dielectric over and contacting at least a portion of the eighth doped region;

an eighth gate structure over and in contact with the eighth gate dielectric; and

a) at least one of the eighth test devices having an eighth contact over and contacting at least a portion of both the eighth gate structure and the eighth doped region; and

b) at least one of the eighth test devices having an eighth contact over and contacting the eighth doped region but not contacting either the eighth gate dielectric or the eighth gate structure.

15. The method of claim 13 further comprises providing and scanning at least two test structures.

16. The method of claim 13 further comprises:

scanning the at least one test structure after contacts are formed but before a first level metal is formed;

forming a first level metal layer contacting said contacts;

electrically testing said at least one test structure to obtain electrical test results; and

correlating the electrical test results and the VC test results to determine which elements of the at least one test structure are defective,

wherein the at least one test structure includes a grounding device.

17. The method of claim 13 further comprises scanning the at least one test structure after contacts are formed and after a first level metal (M1) is formed.

18. The method of claim 13 further comprises:

scanning and visually testing the at least one test structure after contacts are formed but before a first level metal is formed;

forming a first level metal layer contacting said contacts;

electrically testing said at least one test structure to obtain electrical test results; and

correlating the electrical test results and VC test results to determine which elements of the at least one test structure are defective.

19. The method of claim 13 wherein the at least one test structure is comprised of at least:

said first test structure;

said second test structure; and

said seventh test structure;

wherein said test structures are not part of an FET.

20. The method of claim 13 wherein the at least one test structure includes a grounding device comprised of:

a grounding Active Area;

a grounding well region in a contact Active Area; and

a grounding doped region over a grounding well region;

said grounding doped region extending to a surface of said grounding Active Area;

the grounding doped region having a same impurity type as said grounding well region.

21. A method of forming ICs comprising:

providing a test structure which detects various types of leakage defects, the test structure capable of quantifying magnitude of leakage based on grey scale;

differentiating killer leakage defects;

determining a solution for the killer defects; and

fabricating ICs incorporating the solution.