TRENCH GATE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20090057757A1
• Filed: 08/27/2008
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hokomoto, Yoshitaka, Hara, Takuma
• Granted Patent: US 8,169,021 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Disclosed is a trench gate semiconductor device including: a semiconductor layer having a first conductivity type; a first diffusion region having a second conductivity type having a planar structure on the semiconductor layer; a second diffusion region having the first conductivity type positioned selectively on the first diffusion region; a gate electrode provided via a gate insulation film in each first trench facing the second diffusion region and penetrating through the first diffusion region to reach the semiconductor layer; a first semiconductor region of the second conductivity type provided at a position, in the semiconductor layer, apart in a lateral direction from the first diffusion region; a second semiconductor region of the second conductivity type provided at a position, in the first diffusion region, between the adjacent first trenches; and a main electrode in contact with the semiconductor layer and the second diffusion region.

Claims

1. A trench gate semiconductor device, comprising:

a semiconductor layer of a first conductivity type;

a diffusion region of a second conductivity type formed as a planar structure on the semiconductor layer of the first conductivity type;

a diffusion region of the first conductivity type positioned selectively on an upper side of the diffusion region of the second conductivity type so as to be in contact with the diffusion region of the second conductivity type;

a gate electrode provided in a first trench via a gate insulation film, the first trench being formed in plurality in substantially one direction and each being formed to face the diffusion region of the first conductivity type and to penetrate through the diffusion region of the second conductivity type to reach the semiconductor layer of the first conductivity type; and

a first semiconductor region of the second conductivity type provided at a position, in the semiconductor layer of the first conductivity type, apart in a lateral direction from the diffusion region of the second conductivity type;

a second semiconductor region of the second conductivity type provided at a position, in the diffusion region of the second conductivity type, between adjacent trenches among the first trenches; and

a main electrode formed in contact with the semiconductor layer of the first conductivity type and the diffusion region of the first conductivity type.

2. The trench gate semiconductor device according to claim 1,

wherein the first semiconductor region is formed in plurality substantially in a same horizontal plane to be apart from each other.

3. The trench gate semiconductor device according to claim 2,

wherein the second semiconductor region is formed in a horizontal plane which is substantially same as the horizontal plane of the first semiconductor region.

4. The trench gate semiconductor device according to claim 1,

wherein the main electrode extends in a second trench which is formed in the semiconductor layer of the first conductivity type so as to reach the first semiconductor region.

5. The trench gate semiconductor device according to claim 4,

wherein the first semiconductor region has a first portion having a first impurity concentration and a second portion positioned on the first portion and having a second impurity concentration higher than the first impurity concentration.

6. The trench gate semiconductor device according to claim 1,

wherein the main electrode extends in a third trench which is formed in the diffusion region of the second conductivity type so as to reach the second semiconductor region.

7. The trench gate semiconductor device according to claim 6,

wherein the second semiconductor region has a first portion having a relatively low impurity concentration and a second portion positioned on the first portion and having a relatively high impurity concentration.

8. The trench gate semiconductor device according to claim 1,

wherein the diffusion region of the second conductivity type is formed in an island shape in the semiconductor layer of the first conductivity type in a plane view, and the semiconductor layer of the first conductivity type is further present in an island shape in the diffusion region of the second conductivity type formed in the island shape in the plane view.

9. The trench gate semiconductor device according to claim 8,

wherein the first semiconductor region is provided at a depth position in the semiconductor layer of the first conductivity type which is further present in the island shape in the diffusion region of the second conductivity type in the island shape in the plane view.

10. The trench gate semiconductor device according to claim 8,

wherein the first semiconductor region is provided at a depth position in the semiconductor layer of the first conductivity type which is positioned outside the diffusion region of the second conductivity type in the island shape.

11. The trench gate semiconductor device according to claim 1,

wherein the second semiconductor region is provided at a substantially center position between the adjacent trenches.

12. The trench gate semiconductor region according to claim 6,

wherein the main electrode is in contact with the diffusion region of the first conductivity type only along a sidewall of the third trench.

13. The trench gate semiconductor device according to claim 1,

wherein the first conductivity type is an n-type and the second conductivity type is a p-type.

14. The trench gate semiconductor device according to claim 1, further comprising:

a semiconductor substrate of the first conductivity type provided on a side, of the semiconductor layer of the first conductivity type, opposite a side where the diffusion region of the second conductivity type is provided; and

a second main electrode provided on a side, of the semiconductor substrate of the first conductivity type, opposite a side where the semiconductor layer of the first conductivity type is provided.

15. The trench gate semiconductor device according to claim 1,

wherein the first trench is formed in the plurality substantially in the one direction, and the first trench is further formed in plurality in a direction orthogonal to the one direction.

16. The trench gate semiconductor device according to claim 7,

wherein the second portion of the semiconductor region is a portion via which the diffusion region of the second conductivity type and the main electrode are configured to be in electrical conductivity with each other.

17. The trench gate semiconductor device according to claim 1,

wherein the main electrode extends in a second trench which is formed in the semiconductor layer of the first conductivity type so as to reach the first semiconductor region;

wherein the first semiconductor region has a first portion having a first impurity concentration and a second portion positioned on the first portion and having a second impurity concentration higher than the first impurity concentration;

wherein the main electrode extends in a third trench which is formed in the diffusion region of the second conductivity type so as to reach the second semiconductor region;

wherein the second semiconductor region has a first portion having a relatively low impurity concentration and a second portion positioned on the first portion and having a relatively high impurity concentration; and

wherein the second portion of the first semiconductor region and the second portion of the second semiconductor region are provided in a substantially same horizontal plane.

18. The trench gate semiconductor device according to claim 1,

wherein the first semiconductor region and the second semiconductor region are regions simultaneously formed by a same implantation process.

19. A method of manufacturing a trench gate semiconductor device, the method comprising:

forming a diffusion region of a second conductivity type as a planar structure on an upper side of a semiconductor layer of a first conductivity type;

forming a diffusion region of the first conductivity type selectively on an upper side of the diffusion region of the second conductivity type;

forming a trench having a sidewall, part of which is open to the diffusion region of the first conductivity type, and penetrating through the diffusion region of the second conductivity type to reach the semiconductor layer of the first conductivity type;

forming, in the trench, a gate insulation film and a gate electrode surrounded by the gate insulation film;

forming a first semiconductor region of the second conductivity type at a position which is in a deep portion of the semiconductor layer of the first conductivity type and is in a lateral-direction outer side of the diffusion region of the second conductivity type; and

forming a second semiconductor region of the second conductivity type in a deep portion of the diffusion region of the second conductivity type so as to be apart from the gate insulation film and the gate electrode, the second semiconductor region having a higher impurity concentration than an impurity concentration of a surrounding area.

20. The method according to claim 19,

wherein the forming the first semiconductor region and the forming the second semiconductor region are carried out simultaneously as impurity implantation.