PARTITIONED THROUGH-LAYER VIA AND ASSOCIATED SYSTEMS AND METHODS

• US 20090057912A1
• Filed: 09/28/2007
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kheng, Lee Teck
• Granted Patent: US 7,830,018 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 13/00 Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/09645 Patterning on via walls; Plural lands around one hole
• CPC Class Codes: H05K 2201/09854 Hole or via having special cross-section, e.g. elliptical
• CPC Class Codes: H05K 3/4602 characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• CPC Class Codes: Y10T 29/49147 Assembling terminal to base

Abstract

Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.

Claims

1. A substrate, comprising:

a non-conductive layer having a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section and a second section; and

a partitioned via including a first metal interconnect within the via hole on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall, wherein the second metal interconnect is electrically isolated from the first metal interconnect.

2. The substrate of claim 1 wherein the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.

3. The substrate of claim 2 wherein the gap is at least partially filled with a dielectric material.

4. The substrate of claim 2 wherein the gap is defined by at least two partitions cut through the sidewall of the via hole.

5. The substrate of claim 4 wherein the first metal interconnect comprises a first portion of a metal layer and the second metal interconnect comprising a second portion of the metal layer.

6. The substrate of claim 5 wherein the metal layer is further located on at least one of a top-side portion and a bottom-side portion of the non-conductive layer.

7. The substrate of claim 6, further comprising a metal lead land formed in the metal layer and located on at least one of the top-side and bottom-side portions of the non-conductive layer, the metal lead land at least partially surrounding the via and having a first portion that is coupled to the first interconnect and a second portion that is coupled to the second interconnect, the first portion of the lead land being electrically isolated from the second portion of the lead land by the individual partitions.

8. The substrate of claim 7, further comprising a metal trace formed in the metal layer and located on at least one of the top-side and bottom-side portions of the non-conductive layer, the metal trace coupled to the first portion of the lead land.

9. The substrate of claim 7, further comprising a stacking layer having a metal contact that is attached to and substantially aligned with the lead land.

10. The substrate of claim 1, further comprising a stacking layer attached to at least one of a top-side portion and a bottom-side portion of the non-conductive layer, the partitioned via further extending through at least a portion of the stacking layer.

11. A circuit board comprising a partitioned via having:

a sidewall through a dielectric layer defining an opening;

a first metal interconnect within the opening; and

a second metal interconnect within the opening and electrically isolated from the first interconnect, wherein the first and second interconnects are formed from a common metal layer deposited onto the sidewall.

12. The circuit board of claim 11 wherein the via further comprises a dielectric plug, and wherein the first and second interconnects contact separate portions of the dielectric plug.

13. The circuit board of claim 12 wherein the plug includes a partition region that separates the first interconnect from the second interconnect.

14. The circuit board of claim 13, further comprising a segmented metal lead land at least partially surrounding at least one of a top-side portion and a bottom-side portion of the via, wherein individual segments of the lead land are separated from each other by the partition region.

15. A computing system, comprising a processor, a memory, and at least one of an input device and an output device, wherein the computing system includes the circuit board according to claim 11.

16. An interconnect system, comprising:

a circuit board layer having a surface and a via hole that extends through the circuit board layer;

a metal contact at the surface of the circuit board layer, wherein the metal contact at least partially surrounds the via hole, and the metal contact is electrically coupled to an opposing surface of the circuit board layer through the via hole and has a first portion and a second portion electrically isolated from the first portion;

a first metal trace attached to the circuit board layer and coupled to the first portion of the metal contact; and

a second metal trace attached to the circuit board layer and coupled to the second portion of the metal contact.

17. The interconnect system of claim 16 wherein the first and second metal traces are located on opposite sides of the circuit board layer.

18. The interconnect system of claim 16 wherein the first and second metal traces are located on the same side of the circuit board layer and wherein the first metal trace is at least substantially parallel to the second metal trace.

19. The interconnect system of claim 16, further comprising a metal plating layer that at least partially covers a sidewall of the via hole, is electrically coupled to the first portion of the metal contact, and is electrically isolated from the second portion of the metal contact.

20. A method for manufacturing a substrate, the method comprising:

forming a hole through a non-conductive layer, the hole including a sidewall;

depositing a conductive layer on at least a portion of the sidewall; and

forming partitions within the hole that separate the conductive layer into a first interconnect within the hole and a second interconnect within the hole that is electrically isolated form the first interconnect.

21. The method of claim 20 wherein the non-conductive layer comprises at least one of a dielectric core layer of a circuit board and a semiconductor layer of a semiconductor wafer.

22. The method of claim 20 wherein forming the hole and the partitions comprises removing conductive material from the conductive layer using a patterning process that includes at least one of chemical etching, mechanical drilling, laser drilling, and mechanical stamping.

23. The method of claim 20, further comprising at least partially filling the hole with a dielectric spacer material.

24. The method of claim 20 furthering comprising:

depositing the conductive layer on at least one of a top-side and a bottom-side of the non-conductive layer; and

forming a lead land on at least one of a top-side portion and a bottom-side portion of the conductive layer, the lead land at least partially surrounding the hole and including first and second segmented portions, the first segmented portion being electrically coupled to the first interconnect and the second segmented portion being electrically coupled to the second interconnect and electrically isolated from the first interconnect.

25. The method of claim 24 further comprising forming a first trace on at least one of the top-side and bottom-side portions of the conductive layer, the first trace being electrically coupled to the first segmented portion of the lead land.

26. The method of claim 25 further comprising forming a second trace on at least one of the top-side and bottom-side portions of the conductive layer, the second trace being electrically coupled to the second segmented portion of the lead land.

27. The method of claim 26 wherein the first and second traces are located on the same side of the non-conductive layer and are substantially parallel to one another.

28. The method of claim 20 wherein forming the hole further includes forming the hole through a portion of a stacking layer that is attached to the non-conductive layer.

29. A method for electrically routing component contacts of one or more electronic components using a circuit board system of one or more circuit board layers, the method comprising:

coupling a first contact of a component to a first exposed contact of a circuit board layer associated with a circuit board system, the first exposed contact being coupled to a first signal path of the circuit board system routed through a via hole in at least one dielectric layer of the circuit board system; and

coupling a second contact of the component to a second exposed contact of the circuit board layer, the second exposed contact being coupled to a second signal path of the circuit board system routed through the via hole and electrically isolated from the first signal path.

30. The method of claim 29 wherein the via hole includes a first sidewall section covered with a first wall plating and a second sidewall section covered with a second wall plating that is electrically isolated from the first wall plating, the first signal path including the first wall plating and the second signal path including the second wall plating.

31. The method of claim 29 wherein the circuit board system includes at least one set of parallel metal traces that route the first and second signal paths towards the via hole.

32. The method of claim 31 wherein the first and second component contacts are associated with an electronic component that is attached to the circuit board layer.

33. The method of claim 32 wherein the electronic component is configured to transmit a differential signal over the set of parallel traces.

34. The method of claim 29 wherein the first component contact is associated with a first electronic component attached to the circuit board layer and the second component contact is associated with a second electronic component attached to the circuit board layer.