LOW POWER DIGITAL INTERFACE

• US 20090063736A1
• Filed: 11/29/2007
• Published: 03/05/2009
• Est. Priority Date: 08/31/2007
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Wilson, Thomas James, Hori, Yutaka
• Granted Patent: US 8,510,485 B2
• Time in Patent Office: Days
• US Class Current: 710/61
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

This relates to interface circuits for synchronous protocols which do not rely on a dedicated high frequency clock signal. Instead, the interface circuit may rely on a clock signal received over the interface from another device in order to transfer data between the interface and an internal buffer. Furthermore, the interface circuits can rely on a clock signal provided by a bus for a device the interface circuit is located in to transfer data between the internal buffer and the bus. The internal buffer can be, but is not limited to a FIFO. Alternatively, it can be a stack or another data structure. The internal buffer can be configured so that each of its multiple of cells is a shift register. Thus, a preparatory step of moving a byte of data from the buffer to a separate shift register can be avoided.

Claims

1. An interface circuit comprising:

a buffer;

network communication circuitry connected to

the buffer,

a data line of an external network, and

a clock line of an external network configured to transmit a network clock signal; and

a bus communication circuitry connected to

the buffer,

a data line of a bus of a host device comprising the interface circuit, and

a clock line of the bus configured to transmit a bus clock signal,

wherein the network communication circuitry is configured to provide communication between the external network and the buffer based on the network clock signal, and the bus communication circuitry is configured to provide communication from the buffer to the bus based on the bus clock signal, the interface circuit being free of a dedicated internal high frequency clock signal.

2. The interface circuit of claim 1, wherein the buffer comprises a plurality of cells, wherein each cell is a shift register configured to store a plurality of bytes.

3. The interface circuit of claim 1, wherein the network communication circuitry is configured to receive data from the data line of the external network and store the data into the buffer without necessitating any preparatory state updates.

4. The interface circuit of claim 1, wherein the network communication circuitry is configured to store data received from the data line of the external network to the buffer based on the network clock signal, and the bus communication circuitry is configured to read data from the buffer and initialize read portions of the buffer based on the bus clock signal.

5. The interface circuit of claim 1, wherein the network communication circuitry is configured to read data from the buffer and send it over the data line of the external network based on the network clock signal, and the bus communication circuitry is configured to read data from the bus and store it in the buffer based on the bus clock signal.

6. The interface circuit of claim 1, wherein the interface circuit is configured to communicate with a synchronous serial interface.

7. The interface circuit of claim 1, wherein the interface circuit is configured to communicate with an SPI interface.

8. The interface circuit of claim 1, wherein the network clock signal is intermittent.

9. The interface circuit of claim 1, wherein the interface circuit does not generate or utilize any clock signals other than the network and bus clock signals.

10. An electronic device comprising the interface circuit of claim 1.

11. A portable audio player comprising the interface circuit of claim 1.

12. A mobile telephone comprising the interface circuit of claim 1.

13. A flash drive comprising the interface circuit of claim 1.

14. A network of a plurality of electronic devices, wherein at least one of the electronic devices comprises the interface circuit of claim 1.

15. A portable audio player comprising an interface circuit comprising:

a buffer;

network communication circuitry connected to

the buffer,

a data line of an external network, and

a clock line of an external network configured to transmit a network clock signal; and

a bus communication circuitry connected to

the buffer,

a data line of a bus of a host device comprising the interface circuit, and

a clock line of the bus configured to transmit a bus clock signal,

wherein the network communication circuitry is configured to provide communication between the external network and the buffer based on the network clock signal, and the bus communication circuitry is configured to provide communication from the buffer to the bus based on the bus clock signal, the interface circuit being free of a dedicated internal high frequency clock signal.

16. A mobile telephone comprising an interface circuit comprising:

a buffer;

network communication circuitry connected to

the buffer,

a data line of an external network, and

a clock line of an external network configured to transmit a network clock signal; and

a bus communication circuitry connected to

the buffer,

a data line of a bus of a host device comprising the interface circuit, and

a clock line of the bus configured to transmit a bus clock signal,

wherein the network communication circuitry is configured to provide communication between the external network and the buffer based on the network clock signal, and the bus communication circuitry is configured to provide communication from the buffer to the bus based on the bus clock signal, the interface circuit being free of a dedicated internal high frequency clock signal.

17. An interface circuit connected to an external network and a bus and configured to process communications between the external network and the bus, the interface circuit comprising:

a first portion configured to operate according to a clock signal received from the external network; and

a second portion configured to operate according to a clock signal received from the bus,

wherein no part of the interface circuit relies on a dedicated internal high frequency clock signal.

18. The interface circuit of claim 17, wherein no part of the interface circuit relies on any clock signal other than the network and bus clock signals.

20. The method of claim 17, wherein the method is performed without generating or using any clock signals other than the bus and network clock signals.

22. The method of claim 20, wherein the network clock signal is received at around the same time data is received, and the method is performed without performing any preparatory state changes before received data can be saved to the buffer.

19. A method for operating a network interface comprising:

receiving a network clock signal from an external network connection;

receiving data from the external network connection;

saving the received data in a buffer by utilizing the received networked clock signal;

receiving a bus clock signal from a device bus connection; and

reading the received data from the buffer and sending it to the bus connection by utilizing the received bus clock signal,

wherein the method is performed without generating or using an internal dedicated high frequency clock signal.

21. The method of claim 19, wherein the buffer comprises a plurality of cells, each cell being a multi-bit shift register and the saving the received data in the buffer comprises sequentially shifting bits of received data into a cell of the buffer, the shifting being performed according to the network clock signal.

23. A method for operating a network interface comprising:

receiving a bus clock signal from a device bus connection;

receiving data from the bus connection;

saving the received data in a buffer by utilizing the received bus clock signal;

receiving a network clock signal from an external network connection; and

reading the received data from the buffer and sending it to the network connection by utilizing the network clock signal,

wherein the method is performed without generating or using an internal dedicated high frequency clock signal.

24. The method of claim 23, wherein the method is performed without generating or using any clock signals other than the bus and network clock signals.

25. The method of claim 23, wherein the buffer comprises a plurality of cells, each cell being a multi-bit shift register and the reading the received data from the buffer and sending it to the network connection comprises sequentially shifting bits of received data out of a cell of the buffer and sending the bits over the networked connection, the shifting being performed according to the network clock signal.

26. The method of claim 23, wherein the network clock signal is received at around the same time the data is sent over the network connection, and the method is performed without performing any preparatory state changes before data can be sent to the networked connection.