MULTI-CHANNEL MEMORY SYSTEM INCLUDING ERROR CORRECTION DECODER ARCHITECTURE WITH EFFICIENT AREA UTILIZATION

• US 20090063934A1
• Filed: 08/27/2008
• Published: 03/05/2009
• Est. Priority Date: 08/28/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: JO, Namphil
• Granted Patent: US 8,713,417 B2
• Time in Patent Office: Days
• US Class Current: 714/764
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence

Abstract

A memory system includes: a memory controller including an error correction decoder. The error correction decoder includes: a demultiplexer adapted to receive data and demultiplex the data into a first set of data and a second set of data; first and second buffer memories for storing the first and second sets of data, respectively; an error detector; an error corrector; and a multiplexer adapted to multiplex the first set of data and the second set of data and to provide the multiplexed data to the error corrector. While the error corrector corrects errors in the first set of data, the error detector detects errors in the second set of data stored in the second buffer memory.

Claims

1. A memory system, comprising:

at least two memory devices; and

a memory controller having at least first and second communication channels each for communicating data with at least one of the memory devices, the memory controller comprising,

at least first and second error detectors corresponding to the first and second communication channels and each adapted to detect errors in data sets received via the corresponding communication channel from at least one of the memory devices; and

an error corrector adapted to correct errors detected by each of the at least first and second error detectors.

2. The memory system of claim 1, wherein the memory controller further comprises a multiplexer for multiplexing error detection information from the first and second error detectors and passing the multiplexed error detection information to the error corrector.

3. The memory system of claim 1, wherein the memory controller further comprises:

a first buffer adapted to store a first data set received from the first communication channel;

a second buffer adapted to store a second data set received from the second communication channel;

a multiplexer for multiplexing first and second error detection information for the first and second data sets produced by the first and second error detectors; and

an error location identifier for determining error locations within the first and second data sets using the multiplexed first and second error detection information.

4. The memory system of claim 3 wherein the error location identifier determines error locations within the first and second data sets at the same time.

5. The memory system of claim 3, further comprising:

a third buffer adapted to store a third data set received from the first communication channel subsequent to the first data set;

a fourth buffer adapted to store a fourth data set received from the second communication channel subsequent to the second data set,

wherein the error location identifier determines error locations within the first and second data sets while the first and second error detectors detect errors in the third and fourth data sets, respectively.

6. The memory system of claim 5, further comprising a demultiplexer for demultiplexing error location identification information for the first and second data sets from the error location identifier.

7. The memory system of claim 1, wherein the first error detector calculates a first syndrome value of a first data set received via the first communication channel, and wherein the second error detector calculates a second syndrome value of a second data set received via the second communication channel.

8. The memory system of claim 7, further comprising:

a multiplexer for multiplexing the first and second syndrome values; and

an error location identifier for determining error locations within the first and second data sets using the first and second syndrome values, and providing the error location information to the error corrector.

9. The memory system of claim 8, wherein the error location identifier comprises:

a key equation solver;

a Chien-search algorithm block; and

an error evaluator.

10. The memory system of claim 8, further comprising at least first, second, third, and fourth buffers, wherein the error location identifier identifies and corrects errors in the second data set in the second buffer while corrected data of the first data set in the first buffer is transmitted to a host device, and at a same time, while a third data set received via the first communication channel is stored in the third buffer and a fourth data set received via the second communication channel is stored in the fourth buffer.

11. The memory system of claim 1, wherein the first error detector calculates first branch metrics of a first data set received via the first communication channel, and wherein the second error detector calculates second branch metrics of a second data set received via the second communication channel.

12. The memory system of claim 11, further comprising a multiplexer for multiplexing the first and second branch metrics and providing the multiplexed first and second branch metrics to the error corrector.

13. The memory system of claim 11, wherein the error corrector comprises:

an add-compare-select block;

a state metrics memory; and

a survivor path memory.

14. A memory system, comprising:

a memory controller having a first input port for communication with a first memory device via a first communication channel, a second input port for communication with a second memory device via a second communication channel, and an error decoder that is multiplexed for decoding data received from both the first and the second communication channels.

15. The memory system of claim 14, wherein the error decoder is a block code decoder.

16. The memory system of claim 15, wherein the error decoder further comprises:

a first syndrome computation block for calculating a first syndrome value for the data received via the first communication channel;

a second syndrome computation block for calculating a second syndrome value for the data received via the second communication channel;

an error location identifier for determining error locations within the data received via the first and second communication channels using the first and second syndrome values; and

a multiplexer having two inputs and an output, one input being connected to an output of each of the first and second syndrome computation blocks, and the output being connected to an input of the error location identifier,

wherein the first syndrome computation block calculates the first syndrome value for the data received via the first channel while the second syndrome computation block calculates the second syndrome value for the data received via the second channel.

17. The memory system of claim 16, further comprising an error corrector for correcting errors in the data received via the first and second communication channels using the error location information from the error location identifier.

18. The memory system of claim 14, wherein the error decoder is a convolutional decoder.

19. The memory system of claim 18, wherein the error decoder further comprises:

a first branch metrics calculator for calculating branch metrics for the data received via the first channel;

a second branch metrics calculator for calculating branch metrics for the data received via the second communication channel;

an error corrector for correcting errors in the data received via the first and second communication channels; and

a multiplexer having two inputs and an output, one input being connected to an output of each of the first and second branch metrics calculator, and the output being connected to an input of the error corrector,

wherein the first branch metrics calculator calculates the branch metrics for the data received via the first channel while the second branch metrics calculator calculates the branch metrics for the data received via the second channel.

20. A method of processing data received from at least two memory devices via at least two corresponding communication channels, the method comprising:

detecting errors in a first data set received via a first communication channel while detecting errors in a second data set received via a second communication channel; and

correcting the detected errors in the first data set and then subsequently correcting errors in the second data set.

21. The method of claim 20, further comprising detecting errors in a third data set received via the first communication channel while detecting errors in a fourth data set received via the second communication channel also while the errors in the first data set are being corrected.

22. The method of claim 20, wherein detecting the errors in the first and second data sets comprises detecting syndrome values for the first and second data sets.

23. The method of claim 22, further comprising identifying locations of errors in the first data set prior to correcting the errors in the first data set, and identifying locations of errors in the second data set prior to correcting the errors in the second data set.

24. The method of claim 23, wherein identifying the errors in the first data set comprises:

solving a key equation for the first data set;

executing a Chien-search algorithm for the first data set; and

evaluating errors in the first data set.

25. The method of claim 20, wherein detecting the errors in the first and second data sets comprises calculating branch metrics for the first and second data sets.

26. An error decoder, comprising:

at least first and second error detectors corresponding to first and second communication channels and each adapted to detect errors in data sets received via the corresponding communication channel from at least one of memory devices; and

an error corrector adapted to correct errors detected by each of the at least first and second error detectors.

27. The error decoder of claim 26, further comprising a multiplexer for multiplexing error detection information from the first and second error detectors and passing the multiplexed error detection information to the error corrector.

28. The error decoder of claim 26, further comprising:

a first buffer adapted to store a first data set received from the first communication channel;

a second buffer adapted to store a second data set received from the second communication channel;

a multiplexer for multiplexing first and second error detection information for the first and second data sets produced by the first and second error detectors; and

an error location identifier for determining error locations within the first and second data sets using the multiplexed first and second error detection information.

29. The error decoder of claim 28, wherein the error location identifier determines error locations within the first and second data sets at the same time.

30. The error decoder of claim 28, further comprising:

a third buffer adapted to store a third data set received from the first communication channel subsequent to the first data set;

a fourth buffer adapted to store a fourth data set received from the second communication channel subsequent to the second data set,

wherein the error location identifier determines error locations within the first and second data sets while the first and second error detectors detect errors in the third and fourth data sets, respectively.

31. The error decoder of claim 30, further comprising a demultiplexer for demultiplexing error location identification information for the first and second data sets from the error location identifier.

32. The error decoder of claim 26, wherein the first error detector calculates a first syndrome value of a first data set received via the first communication channel, and wherein the second error detector calculates a second syndrome value of a second data set received via the second communication channel.

33. The error decoder of claim 32, further comprising:

a multiplexer for multiplexing the first and second syndrome values; and

an error location identifier for determining error locations within the first and second data sets using the first and second syndrome values, and providing the error location information to the error corrector.

34. The error decoder of claim 33, wherein the error location identifier comprises:

a key equation solver;

a Chien-search algorithm block; and

an error evaluator.

35. The error decoder of claim 34, further comprising at least first, second, third, and fourth buffers, wherein the error location identifier identifies and corrects errors in the second data set in the second buffer while corrected data of the first data set in the first buffer is transmitted to a host device, and at a same time, while a third data set received via the first communication channel is stored in the third buffer and a fourth data set received via the second communication channel is stored in the fourth buffer.

36. The error decoder of claim 26, wherein the first error detector calculates first branch metrics of a first data set received via the first communication channel, and wherein the second error detector calculates second branch metrics of a second data set received via the second communication channel.

37. The error decoder of claim 36, further comprising a multiplexer for multiplexing the first and second branch metrics and providing the multiplexed first and second branch metrics to the error corrector.

38. The error decoder of claim 36, wherein the error corrector comprises:

an add-compare-select block;

a state metrics memory; and

a survivor path memory.