MOS device with schottky barrier controlling layer

• US 20090065814A1
• Filed: 12/21/2007
• Published: 03/12/2009
• Est. Priority Date: 02/11/2005
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Wang, Xiaobin, Bhalla, Anup, Pan, Ji, Wei, Sung-Po
• Granted Patent: US 8,362,547 B2
• Time in Patent Office: Days
• US Class Current: 257/230
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/47 Schottky barrier electrodes H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7806 the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A semiconductor device is formed on a semiconductor substrate. The semiconductor device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and the body into the drain, an active region contact electrode disposed within the active region contact trench, wherein the active region contact electrode and the drain form a Schottky diode, and a Schottky barrier controlling layer disposed in the epitaxial layer adjacent to the active region contact trench.

Claims

1. A semiconductor device formed on a semiconductor substrate, comprising:

a drain;

an epitaxial layer overlaying the drain; and

an active region comprising;

a body disposed in the epitaxial layer, having a body top surface;

a source embedded in the body, extending from the body top surface into the body;

a gate trench extending into the epitaxial layer;

a gate disposed in the gate trench;

an active region contact trench extending through the source and the body into the drain;

an active region contact electrode disposed within the active region contact trench, wherein the active region contact electrode and the drain form a Schottky diode; and

a Schottky barrier controlling layer disposed in the epitaxial layer adjacent to the active region contact trench.

2. The semiconductor device of claim 1, wherein the Schottky barrier controlling layer is disposed adjacent to a lower portion of the active region contact trench.

3. The semiconductor device of claim 1, wherein the Schottky barrier controlling layer includes a thin layer of material doped with opposite polarity dopant as the epitaxial layer.

4. The semiconductor device of claim 1, wherein the Schottky barrier controlling layer comprising a thin layer of narrow bandgap material.

5. The semiconductor device of claim 1, wherein the gate trench is a first gate trench;

and

the device further comprising a gate region comprising;

a second gate trench extending into the epitaxial layer;

a second gate disposed in the gate trench; and

a gate contact trench formed within the second gate.

6. The semiconductor device of claim 5, wherein the gate contact trench and the active region contact trench have approximately the same depth.

7. The semiconductor device of claim 5, wherein the active region contact trench has a different depth than the gate contact trench.

8. The semiconductor device of claim 1, wherein the active region contact trench has a non-uniform depth.

9. The semiconductor device of claim 1, wherein:

the active region contact trench has a first depth and a second depth;

the first depth is shallower than the second depth; and

a first contact opening corresponding to the first depth is wider than a second contact opening corresponding to the second depth.

10. The semiconductor device of claim 1, further comprising an anti-punch through implant disposed on a sidewall of the active region contact trench.

11. The semiconductor device of claim 10, wherein the anti-punch through implant is disposed above the Schottky barrier controlling layer.

12. The semiconductor device of claim 1, further comprising a blanket implant deposited throughout the epitaxial layer, wherein the blanket implant has opposite polarity as the epitaxial layer.

13. The semiconductor device of claim 1, further comprising an epitaxial layer profile tuning implant deposited under the active region contact trench.

14. The semiconductor device of claim 1, further comprising an island region below the active region contact trench, wherein the island region has opposite polarity as the epitaxial layer.

15. The semiconductor device of claim 1, wherein the gate extends above the body top surface.

16. A method of fabricating a semiconductor device, comprising:

forming a gate trench in an epitaxial layer overlaying a semiconductor substrate;

depositing gate material in the gate trench;

forming a body;

forming a source;

forming an active region contact trench that extends through the source and the body into the drain;

depositing a Schottky barrier controlling layer in and

disposing a contact electrode within the active region contact trench.

17. The method of claim 16, wherein depositing the Schottky barrier controlling layer includes depositing a thin layer of material doped with opposite polarity dopant as the epitaxial layer.

18. The method of claim 16, wherein the gate trench is a first gate trench;

and

the method further comprising forming a gate region, including by;

forming a second gate trench extending into the epitaxial layer;

forming a second gate disposed in the gate trench; and

forming a gate contact trench formed within the second gate.

19. The method of claim 18, wherein the gate contact trench and the active region contact trench have approximately the same depth.

20. The method of claim 18, wherein the active region contact trench has a different depth than the gate contact trench.

21. The method of claim 18, wherein the active region contact trench has a non-uniform depth.

22. The method of claim 16, wherein:

the active region contact trench is formed to have a first depth and a second depth;

the first depth is shallower than the second depth; and

a first contact opening corresponding to the first depth is wider than a second contact opening corresponding to the second depth.

23. The method of claim 16, further comprising depositing a blanket implant deposited throughout the epitaxial layer, wherein the blanket implant has opposite polarity as the epitaxial layer.

24. The method of claim 16, further comprising forming an epitaxial layer profile tuning implant deposited under the active region contact trench.

25. The method of claim 16, further comprising forming an island region below the active region contact trench, wherein the island region has opposite polarity as the epitaxial layer.

26. The method of claim 16, wherein the gate is formed to extend above the body top surface.