Method And Apparatus For Testing Devices Using Serially Controlled Resources

• US 20090079448A1
• Filed: 09/25/2007
• Published: 03/26/2009
• Est. Priority Date: 09/25/2007
• Status: Active Grant

• Current Assignee: FormFactor Incorporated
• Original Assignee: FormFactor Incorporated
• Inventors: Berry, Tommie Edward
• Granted Patent: US 7,888,955 B2
• Time in Patent Office: Days
• US Class Current: 324/750.10
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture

Abstract

Methods and apparatus for testing devices using serially controlled resources have been described. Examples of the invention can relate to an apparatus for testing a device under test (DUT). In some examples, an apparatus can include an integrated circuit (IC) having a serialized input coupled to test circuits, the test circuits selectively communicating test signals with the DUT responsive to a test control signal on the serialized input.

Claims

1. An apparatus for testing a device under test (DUT), comprising:

an integrated circuit (IC) having a serialized input coupled to test circuits, the test circuits selectively communicating test signals with the DUT responsive to a test control signal on the serialized input.

2. The apparatus of claim 1, wherein the test circuits comprise:

a shift register, coupled to the serialized input, configured to store bits of the test control signal; and

test resources, coupled to the shift register, configured to provide at least one of a source or a sink of the test signals responsive to the bits.

3. The apparatus of claim 2, wherein each of the test resources comprises one of a digital resource, an analog resource, or a power resource.

4. The apparatus of claim 2, wherein at least one of the test resources is configured to generate a respective at least one of the test signals responsive to at least one of the bits.

5. The apparatus of claim 2, wherein at least one of the test resources is configured to switch a respective at least one of the test signals responsive to at least one of the bits.

6. A probe card assembly, comprising:

at least one serial control line providing a respective at least one test control signal; and

a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to the at least one serial control line, the plurality of ICs selectively communicating test signals between test resources and test probes responsive to the at least one test control signal.

7. The probe card assembly of claim 6, wherein each of the plurality of ICs comprises:

at least one control group, each including;

a shift register configured to store bits of a test control signal of the at least one test control signal; and

a plurality of the test resources, coupled to the shift register, configured to provide at least one of a source or a sink of a plurality of the test signals responsive to the bits.

8. The probe card assembly of claim 7, wherein at least one of the plurality of the test resources is configured to generate a respective at least one of the plurality of the test signals responsive to at least one of the bits.

9. The probe card assembly of claim 7, wherein at least one of the plurality of the test resources is configured to switch a respective at least one of the plurality of the test signals responsive to at least one of the bits.

10. The probe card assembly of claim 6, wherein each of the test resources comprises one of a digital resource, an analog resource, or a power resource.

11. The probe card assembly of claim 6, wherein the at least one serial control line comprises a first serial control line providing a first test control signal and a second serial control line providing a second test control signal, and wherein the test resources in the plurality of ICs comprise a first chain of test resources responsive to the first test control signal and a second chain of test resources responsive to the second test control signal.

12. The probe card assembly of claim 11, wherein the first chain of test resources includes digital resources and the second chain of test resources includes power resources.

13. A test assembly, comprising:

a printed wiring board including connectors for connecting to a test system controller, and at least one serial control line providing a respective at least one test control signal from the test system controller; and

a probe head supporting test probes and at least one integrated circuit (IC) coupled to the at least one serial control line, the at least one IC selectively communicating test signals between test resources and test probes responsive to the at least one test control signal.

14. The test assembly of claim 13, wherein the at least one IC includes a plurality of ICs serially coupled to form a chain, the chain coupled to the at least one serial control line.

15. The test assembly of claim 13, wherein at least one serial control line includes a first serial control line providing a first test control signal and a second serial control line providing a second test control signal, and wherein the test resources in the at least one IC comprise a first chain of test resources responsive to the first test control signal and a second chain of test resources responsive to the second test control signal.

16. The test assembly of claim 15, wherein the first chain of test resources includes digital resources and the second chain of test resources includes power resources.

17. The test assembly of claim 13, wherein each of the test resources comprises one of a digital resource, an analog resource, or a power resource.

18. A method of testing components on a wafer using a probe card assembly, comprising:

serially shifting a test control signal through a chain comprising a plurality of integrated circuits (ICs);

selectively coupling test signals from test resources to test probes responsive to the test control signal;

capturing test result signals at the test resources from the test probes; and

serially reading back from the chain to obtain the test result signals.

19. The method of claim 18, wherein the act of serially shifting comprises, for each of the plurality of ICs:

serially shifting a frame of the test control signal into a shift register; and

parallel shifting bits of the frame into shadow registers coupled to a plurality of the test resources.

20. The method of claim 19, wherein the act of selectively coupling comprises, for each of the plurality of ICs:

generating or switching a plurality of the test signals at the plurality of the test resources responsive to the bits in the shadow registers.

21-32. -32. (canceled)