Memory switching control apparatus using open serial interface, operating method thereof, and data storage device therefor
First Claim
1. A memory switching control apparatus using an open serial interfacing, comprising:
- one or more processor interfacing units which perform interfacing with one or more processing units;
one or more memory interfacing units which respectively have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; and
a plurality of arbitrating units which are provided corresponding to the memory interfacing units to independently arbitrate usage rights of the processor interfacing units to the memory interfacing units.
1 Assignment
0 Petitions
Accused Products
Abstract
Provided is a memory switching control apparatus using an open serial interfacing scheme capable of enhancing flexibility, reliability, availability, performance in a data communication processes between a memory and a processing unit and an operating method thereof. The memory switching control apparatus includes: one or more processor interfacing units which perform interfacing with one or more processing units; one or more memory interfacing units which have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; and a plurality of arbitrating units which are provided corresponding to the memory interfacing units to independently arbitrate usage rights of the processor interfacing units to the memory interfacing units.
24 Citations
25 Claims
-
1. A memory switching control apparatus using an open serial interfacing, comprising:
-
one or more processor interfacing units which perform interfacing with one or more processing units; one or more memory interfacing units which respectively have open-serial-interfacing-scheme memory interfacing ports to interface with data storage devices connected to the memory interfacing ports in a serial interfacing scheme; and a plurality of arbitrating units which are provided corresponding to the memory interfacing units to independently arbitrate usage rights of the processor interfacing units to the memory interfacing units. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
-
-
18. The memory switching control apparatus of 11, wherein the ID is generated by combining information of the processor interfacing unit which issues the memory-accessing request and specific request sequence information of the processor interfacing unit.
-
19. An operating method of a memory switching control apparatus using an open serial interfacing scheme, the memory switching control apparatus having a plurality of processor interfacing units connected to a plurality of processing units, a plurality of memory interfacing units connected to a plurality of data storage devices, and a plurality of arbitrating units arbitrating usage right to the memory interfacing units, the operating method comprising:
-
if an initialization operation is started, driving the memory interfacing units at corresponding lowest speeds so as to check the number of available interfacing lines; checking a highest speed of the checked available interfacing lines; and driving all the checked available interfacing lines at the checked highest speed so as to determine whether or not the available interfacing lines operate normally; measuring data delays between the interfacing lines that are determined to operate normally and compensating for the data delays between the interfacing lines; performing a memory test for data storage devices connected to the normally-operated interfacing lines; and if the result of the memory test is normal, allocating system addressing spaces mapped to the data storage devices to each of the memory interfacing units and registrating thereof in a memory port table. - View Dependent Claims (20, 21, 22, 23, 24)
-
-
25. A data storage device comprising:
-
one or more memory devices; and one or more memory interfacing units, each of which an open-serial-interfacing-scheme memory interfacing port separately or commonly connected to the memory devices, wherein the memory interfacing unit receives a predetermined format of data through interfacing lines connected to the memory interfacing port to transfer the data to the memory devices or converts the data read from the memory devices to the predetermined format of data to output the data to the memory interfacing port.
-
Specification