DYNAMICALLY MANAGING THERMAL LEVELS IN A PROCESSING SYSTEM

• US 20090083551A1
• Filed: 09/25/2007
• Published: 03/26/2009
• Est. Priority Date: 09/25/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cohen, Aviad, Finkelstein, Lev, Rotem, Efraim, Ronen, Ronny
• Granted Patent: US 7,934,110 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G05D 23/1935 using sequential control
• CPC Class Codes: G06F 1/206 comprising thermal management

Abstract

A technique to dynamically maintain the thermal levels of a plurality of cores of a processing system by interleave core hopping with throttling techniques. The interleaving logic may transfer execution of threads from a hot core to a cold if core hopping is applicable. Core hopping may be applicable if there exist a cold core to which the execution of threads can be assigned to from a hot core and if the rate of occurrence of core hopping is within an allowable rate value. The interleaving logic may apply throttling techniques if core hopping is not applicable. The throttling techniques may throttle the throttling parameters, which may comprise voltage, frequency, and micro-architecture throttling parameters provided to the hot core if the core hopping is not applicable.

Claims

1. An apparatus comprising:

a sensor logic to generate a thermal interrupt, and

an interleaving logic coupled to the sensor logic, wherein the interleaving logic is to maintain thermal level of a plurality of cores by interleaving core hopping with throttling techniques.

2. The apparatus of claim 1 further comprises a core hopping logic coupled to the interleaving logic, wherein the core hopping logic is to transfer execution of threads from a first core to a second core upon receiving a core hop signal generated by the interleaving logic, wherein the plurality of cores comprise the first core and the second core.

3. The apparatus of claim 2, wherein the interleaving logic is to generate the core hop signal if core hopping is applicable, wherein the interleaving logic is to determine whether core hopping is applicable in response to receiving the thermal interrupt.

4. The apparatus of claim 3, wherein the interleaving logic is to determine that core hopping is applicable if thermal level of the first core exceeds a hot threshold value and thermal level of the second core is less than a cold threshold value and rate of occurrence of core hopping is less than an allowable rate value.

5. The apparatus of claim 1 further comprises a throttling logic coupled to the interleaving logic, wherein the throttling logic is to scale the throttling parameters provided to the first core in response to receiving a thermal trigger, if core hopping is not applicable.

6. The apparatus of claim 5, wherein the throttling parameters comprise voltage, frequency, and micro-architecture throttling parameters.

7. The apparatus of claim 6, wherein the interleaving logic is to determine that core hopping is not applicable if thermal level of the second processing core is more than a cold threshold value and rate of occurrence of core hopping is more than an allowable rate value.

8. The apparatus of claim 1 further comprises a throttling logic coupled to the interleaving logic, wherein the throttling logic is to scale the throttling parameters provided to the first core in response to occurrence of a time-based event, while core hopping is not applicable.

9. The apparatus of claim 8, wherein the throttling parameters comprise voltage, frequency, and micro-architecture throttling parameters.

10. The apparatus of claim 1, wherein the interleaving logic is to keep the throttling active if the thermal value of the first core exceeds the hot threshold value.

11. A method comprising:

generating a thermal interrupt, and

maintaining thermal level of a plurality of cores by interleaving core hopping with throttling techniques.

12. The method of claim 11 further comprises transferring execution of threads from a first core to a second core upon receiving a core hop signal, wherein the plurality of cores comprise the first core and the second core.

13. The method of claim 12 comprises generating the core hop signal if core hopping is applicable, wherein whether core hopping is applicable is determined in response to receiving the thermal interrupt.

14. The method of claim 13 comprises determining that core hopping is applicable if thermal level of the first core exceeds a hot threshold value and thermal level of the second core is less than a cold threshold value and rate of occurrence of core hopping is less than an allowable rate value.

15. The method of claim 11 further comprises scaling of throttling parameters provided to the first core in response to receiving a thermal trigger if core hopping is not applicable.

16. The method of claim 15, wherein throttling parameters comprise voltage, frequency, and micro-architecture throttling parameters.

17. The method of claim 16 comprises determining that core hopping is not applicable if thermal level of the second processing core is more than a cold threshold value and rate of occurrence of core hopping is more than an allowable rate value.

18. The method of claim 11 further comprises scaling of throttling parameters provided to the first core in response to occurrence of a time-based event, while core hopping is not applicable.

19. The method of claim 18, wherein throttling parameters comprise voltage, frequency, and micro-architecture throttling parameters.

20. The method of claim 11 comprises keeping the throttling technique active if the thermal value of the first core exceeds a hot threshold value.