THREE DIMENSIONAL STRAINED QUANTUM WELLS AND THREE DIMENSIONAL STRAINED SURFACE CHANNELS BY GE CONFINEMENT METHOD

• US 20090085027A1
• Filed: 09/29/2007
• Published: 04/02/2009
• Est. Priority Date: 09/29/2007
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jin, Been-Yih, Chau, Robert S., Kavalieros, Jack T., Doyle, Brian S.
• Granted Patent: US 7,767,560 B2
• Time in Patent Office: Days
• US Class Current: 257/24
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

The present disclosure describes a method and apparatus for implementing a 3D (three dimensional) strained high mobility quantum well structure, and a 3D strained surface channel structure through a Ge confinement method. One exemplary apparatus may include a first graded SiGe fin on a Si substrate. The first graded SiGe fin may have a maximum Ge concentration greater than about 60%. A Ge quantum well may be on the first graded SiGe fin and a SiGe quantum well upper barrier layer may be on the Ge quantum well. The exemplary apparatus may further include a second graded SiGe fin on the Si substrate. The second graded SiGe fin may have a maximum Ge concentration less than about 40%. A Si active channel layer may be on the second graded SiGe fin. Other high mobility materials such as III-V semiconductors may be used as the active channel materials. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

Claims

1. A semiconductor device, comprising:

a Si_1-yGe_y fin on a Si substrate, said Si_1-yGe_y fin having a maximum Ge concentration, y, greater than about 60%;

a quantum well on said Si_1-yGe_y fin, wherein said quantum well is uniaxially compressively strained; and

a Si_1-yGe_y quantum well upper barrier layer on said quantum well.

2. The semiconductor device of claim 1, further comprising:

a Si_1-zGe_z fin on said Si substrate, said Si_1-zGe_z fin having a maximum Ge concentration, z, less than about 40%; and

an active channel layer on said Si_1-zGe_z fin wherein, said active channel layer is uniaxially tensile strained.

3. The semiconductor device of claim 1, wherein said maximum Ge concentration, y, is between about 60% and about 90%.

4. The semiconductor device of claim 2, wherein said maximum Ge concentration, z, is between about 10% and about 40%.

5. The semiconductor device of claim 1, further comprising:

an Si cap on said Si_1-yGe_y quantum well upper barrier layer.

6. The semiconductor device of claim 1, wherein said quantum well is Ge, GaAs, InGaAs, or InSb.

7. The semiconductor device of claim 2, wherein said active channel layer is Si, GaAs, InGaAs, or InSb.

8. The semiconductor device of claim 1, wherein said Si_1-yGe_y fin is self-graded.

9. The semiconductor device of claim 2, wherein said Si_1-yGe_y fin is self-graded.

10. A method of forming a semiconductor device on an Si substrate, said method comprising:

forming a Si fin structure on said Si substrate, by protecting with photoresist a portion of said Si substrate where said Si fin structure is to be formed and etching away adjacent regions of said Si substrate;

growing a layer of oxide on said Si fin structure and said Si substrate;

exposing at least a portion of said Si fin structure by mechanically or chemically polishing said oxide layer to a top surface of said Si fin structure and recessing said oxide layer adjacent said Si fin structure;

epitaxially growing a Si_1-xGe_x layer on said exposed portion of said Si fin structure wherein said Si_1-xGe_x layer has a first Ge concentration, x; and

preferentially oxidizing Si from said Si_1-xGe_x layer and from said Si fin structure into SiO₂ wherein Si is predominantly consumed and Ge is forced into said Si fin structure resulting in a Si_1-wGe_w fin structure having a maximum second Ge concentration, w, and a maximum width.

11. The method of claim 10 wherein:

said first Ge concentration, x, is in the range of about 10% to about 30%.

12. The method of claim 10 wherein:

said first Ge concentration, x, is in the range of about 5% to about 20%.

13. The method of claim 10 wherein:

said maximum second Ge concentration is in the range of about 60% to about 90%.

14. The method of claim 12 wherein:

said maximum second Ge concentration is in the range of about 10% to about 40%.

15. The method of claim 13, further comprising:

selectively epitaxially growing a quantum well on said Si_1-wGe_w fin structure wherein said quantum well is uniaxially compressively strained; and

epitaxially growing a Si_1-wGe_w upper quantum well barrier layer on said quantum well.

16. The method of claim 14, further comprising:

selectively epitaxially growing an active channel layer on said Si_1-wGe_w fin structure wherein said active channel layer is uniaxially tensile strained.

17. The method of claim 10 wherein said width is less than about 30 nm.

18. The method of claim 15 further comprising epitaxially growing an Si cap on said Si_1-wGe_w upper quantum well barrier layer.