FPGA configuration protection and control using hardware watchdog timer

• US 20090085603A1
• Filed: 09/27/2007
• Published: 04/02/2009
• Est. Priority Date: 09/27/2007
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Network Communications Incorporated (Fujitsu Limited)
• Inventors: Paul, Steven, Garcia, Arturo, Capellaro, Mark
• Granted Patent: US 7,971,051 B2
• Time in Patent Office: Days
• US Class Current: 326/8
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

An apparatus and method provides automatic reconfiguration of an FPGA, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided that does not require the use of additional devices. An apparatus for FPGA configuration protection comprises watchdog signal generator circuitry in the FPGA configured to output a watchdog signal when the FPGA is properly configured and watchdog circuitry configured to receive the watchdog signal and to initiate reconfiguration of the FPGA if the watchdog signal is not received for or within a predetermined time. The circuitry in the FPGA may be configured to receive a signal from a processor and to output the watchdog signal when the signal from the processor is received.

Claims

1. An apparatus for FPGA configuration protection comprising:

watchdog signal generator circuitry in the FPGA configured to output a watchdog signal when the FPGA is properly configured; and

watchdog circuitry configured to receive the watchdog signal and to initiate reconfiguration of the FPGA if the watchdog signal is not received for or within a predetermined time.

2. The apparatus of claim 1, wherein the watchdog circuitry is external to the FPGA.

3. The apparatus of claim 1, wherein the watchdog circuitry comprises a timer.

4. The apparatus of claim 1, further comprising circuitry in the FPGA configured to receive a signal from a processor and to output the watchdog signal when the signal from the processor is received.

5. A method of FPGA configuration protection comprising:

initiating configuration of the FPGA;

upon successful completion of configuration of the FPGA, outputting a signal from the FPGA;

if the signal from the FPGA is received, not initiating reconfiguration of the FPGA; and

if the signal from the FPGA is not received for or within a predetermined time, initiating reconfiguration of the FPGA.

6. The method of claim 5, further comprising:

receiving a signal from a processor; and

outputting the signal from the FPGA when the signal from the processor is received.