POWER SUPPLY SYSTEM FOR LOW POWER MCU

• US 20090089599A1
• Filed: 10/01/2007
• Published: 04/02/2009
• Est. Priority Date: 10/01/2007
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: VOGEL, GABRIEL, SHANNON, DONELSON A., GUO, XIAOLING, WEI, DAZHI, WESTWICK, ALAN L.
• Granted Patent: US 7,908,500 B2
• Time in Patent Office: Days
• US Class Current: 713/323
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microcontroller includes a processing unit having a processing unit having normal power mode of operation and a low power mode of operation. The processing unit further having digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values. A plurality of retention flip-flops are associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation. The plurality of retention flip flops include a first type of transistors for operating in both the low and high power modes of operation and a second type of transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the second type of transistors.

Claims

1. A microcontroller unit, comprising:

a processing unit having normal power mode of operation and a low power mode of operation and having;

digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values;

a plurality of retention flip-flops associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation; and

wherein the plurality of retention flip flops include a first type of transistors for operating in both the low and high power modes of operation and a second type of transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the second type of transistors.

2. The microcontroller unit of claim 1, wherein the first type of transistors comprises core transistors and the second type of transistors comprises input/output transistors.

3. The microcontroller unit of claim 1, wherein the first type of transistors comprises thick oxide transistors and the second type of transistors comprises thin oxide transistors.

4. The microcontroller unit of claim 1, wherein the plurality of retention flip-flops further comprises:

a master latch circuit comprised of the first type of transistor for latching digital circuit values in the normal power mode of operation;

a driver circuit comprised of the first type of transistors for driving an output of the retention flip-flops in the normal power mode of operation; and

a slave latch circuit comprised of the second type of transistor for latching the digital circuit values in the low power mode of operation.

5. The microcontroller unit of claim 1, wherein the retention flip flops are integral and part of the digital circuitry utilized in the processing of digital values.

6. The microcontroller unit of claim 1, wherein the retention flip flops are disposed in between data and input to an associated one of the logic circuits on an output of an associated one of the logic circuits.

7. A microcontroller unit, comprising:

a processing unit having normal power mode of operation and a low power mode of operation and having;

digital circuitry connected to the processing unit having a plurality of logic circuits associated therewith for processing digital values;

a plurality of retention flip-flops associated with the digital circuitry for storing a logical state of at least one or more of the logic circuits within the digital circuitry when the processing unit enters the low power mode of operation; and

wherein the plurality of retention flip flops include core transistors for operating in both the low and high power modes of operation and input/output transistors for operation only in the normal mode of operation and wherein substantially the remainder of the digital circuitry in the processing unit comprises the input/output transistors.

8. The microcontroller unit of claim 7, wherein the core transistors comprises thick oxide transistors and the input/output transistors comprises thin oxide transistors.

9. The microcontroller unit of claim 7, wherein the plurality of retention flip-flops further comprises:

a master latch circuit comprised of the core transistors for latching digital circuit values in the normal power mode of operation;

a driver circuit comprised of the core transistors for driving an output of the retention flip-flops in the normal power mode of operation; and

a slave latch circuit comprised of the input/output transistors for latching the digital circuit values in the low power mode of operation.

10. The microcontroller unit of claim 7, wherein the retention flip flops are integral and part of the digital circuitry utilized in the processing of digital values.

11. The microcontroller unit of claim 7, wherein the retention flip flops are disposed in between data and input to an associated one of the logic circuits on an output of an associated one of the logic circuits.

12. A retention flip-flop circuit, comprising:

a first type of transistors for operating in both the low and high power modes of operation;

a second type of transistors for operation only in the normal mode of operation;

wherein responsive to entry into a low power mode of operation the second type of transistors store a logical state of the flip-flop circuit; and

wherein in the normal power mode of operation the first type of transistors are active and the second type of transistors are active and in the low power mode of operation the second type of transistors are active and the first type of transistors are inactive.

13. The retention flip-flop circuit of claim 12, wherein the first type of transistors comprises core transistors and the second type of transistors comprises input/output transistors.

14. The retention flip-flop circuit of claim 12, wherein the first type of transistors comprises thick oxide transistors and the second type of transistors comprises thin oxide transistors.

15. The retention flip-flop circuit of claim 12, wherein the plurality of retention flip-flops further comprises:

a master latch circuit comprised of the first type of transistors for latching digital circuit values in the normal power mode of operation;

a driver circuit comprised of the first type of transistors for driving an output of the retention flip-flops in the normal power mode of operation; and

a slave latch circuit comprised of the second type of transistor for latching the digital circuit values in the low power mode of operation.