Multi-resolution Image Sensor Array with High Image Quality Pixel Readout Circuitry

• US 20090091648A1
• Filed: 10/09/2007
• Published: 04/09/2009
• Est. Priority Date: 10/09/2007
• Status: Abandoned Application

• Current Assignee: CMOS Sensor, Inc.
• Original Assignee: CMOS Sensor, Inc.
• Inventors: Lin, Shengmin, Wang, Weng-Lyang
• Application Number:
  US11/869,732
• Publication Number:
  US 20090091648A1
• Time in Patent Office: Days
• US Class Current: 348/301
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/60 Noise processing, e.g. detecting, correcting, reducing or removing noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

A configurable, compact multi-resolution linear image sensor array is disclosed. The multi-resolution image sensor array employs a spatial array of photoelectric sites with each site having an image output terminal and a cluster of switched photo-detector elements. To effect a high quality snapshot operation mode for a high pixel count array, a transfer control switch is added bridging each photo-detector element and its correspondingly connected negative input terminal of an operational amplifier to form an active pixel sensor circuit. To minimize a reset kTC noise associated with numerous traditional active pixel sensor circuits, an in-pixel KTC noise-correlated correlated multiple sampling (CMS) circuitry is also proposed to replace an otherwise traditional correlated double sampling (CDS) circuitry.

Claims

1. A multi-resolution image sensor array for converting an incoming image light into a corresponding array of image signals, the multi-resolution image sensor array comprises a spatial array of photoelectric sites PES_j (j=1, 2, . . . , M with M>

=2) for converting the incoming image light into the array of image signals, wherein each PES_j further comprises;

a) an image output terminal IOT_j; and

b) a cluster of switched photo-detector elements SPE_k (k=1, 2, . . . , N with N>

=2) each having;

b1) a photo-detector element PE_k, having an elemental detector output terminal EDOT_k and a photo-detector face PF_k of pre-determined shape and size for sensing the incoming image light at a corresponding elemental spatial resolution, for converting the incoming image light into an elemental detector output signal EDOS_k and delivering it through the EDOT_k; and

b2) a transfer control switch TCS_K in series connection with the PE_k and the IOT_j for,

b21) upon switch open, converting the incoming image light into the EDOS_k with the PE_k; and

,

b22) upon switch closure, transferring the EDOS_k from the EDOT_k to the IOT_j

whereby, corresponding to a pre-determined multitude of combinations of switch closures amongst the TCS_K (k=1, 2, . . . , N), the multi-resolution image sensor array converts the incoming image light into the array of image signals at a corresponding multitude of spatial resolutions.

2. The multi-resolution image sensor array of claim 1 wherein the pre-determined multitude of combinations of switch closures amongst the TCS_K (k=1, 2, . . . , N) is further selected such that the multi-resolution image sensor array converts the incoming image light into the array of image signals with a corresponding multitude of pixel shapes.

3. The multi-resolution image sensor array of claim 1 wherein said photo-detector element PE_k is a photoconductor, a photodiode, a photoelectric PIN diode or a high dynamic range photo sensor.

4. A high image quality pixel readout circuitry for converting an incoming image light pixel into a corresponding output video signal, the high image quality pixel readout circuitry comprises:

a) an operational amplifier having a positive input terminal, a negative input terminal, an output terminal and a feedback loop circuit coupling the output terminal to the negative input terminal, said feedback loop circuit further configured to convert an inbound photoelectric signal at the negative input terminal into an outbound photoelectric signal at the output terminal;

b) a photodiode exposed to the incoming image light pixel, said photodiode having its anode grounded thus accumulating, through its cathode, a charge signal responsive to said incoming image light pixel; and

c) a transfer control switch bridging the photodiode cathode and the negative input terminal, said transfer control switch being;

c1) set open during a charge accumulation period wherein the charge signal gets accumulated on the photodiode cathode; and

c2) set closed during a charge transfer period wherein the thus accumulated charge signal gets transferred into the inbound photoelectric signal at the negative input terminal and converted into the outbound photoelectric signal at the output terminal

whereby, when the high image quality pixel readout circuitry gets replicated into a multi-pixel image sensor array of high pixel count and with sequential video signal readout, an otherwise image-degrading effect of inter-pixel differential leakage of the charge signal through the operational amplifier can be substantially reduced with proper sequencing of the corresponding array of transfer control switches thus effecting a snapshot operation mode.

5. The high image quality pixel readout circuitry of claim 4 wherein said operational amplifier is a resettable capacitive trans-impedance amplifier (CTIA) with the feedback loop circuit further comprises a parallel connection of:

a charge integration capacitor for converting, through time integration, a photoelectric current from the photodiode into a photoelectric voltage at the output terminal; and

a loop-reset switch that;

upon its opening, allows ongoing time integration of the photoelectric current from the photodiode into the photoelectric voltage at the output terminal;

whereas

upon its closing forces a complete signal reset of the photodiode and the operational amplifier.

6. The high image quality pixel readout circuitry of claim 5 further comprises an in-pixel correlated double sampling (CDS) circuit having:

an input end being connected to the output terminal of said operational amplifier; and

a following parallel connection of;

a switched image sampling branch having an image signal storage capacitor plus a plurality of image multiplexing switches for providing a sampled image signal corresponding to said photoelectric voltage at the output terminal; and

a switched reset sampling branch having a reset signal storage capacitor plus a plurality of reset multiplexing switches for providing a sampled reset signal corresponding to a reset voltage at the output terminal

whereby allows the desired output video signal to be extracted as the difference between the sampled image signal and the sampled reset signal with an external difference amplifier attached to said in-pixel CDS circuit.

7. The high image quality pixel readout circuitry of claim 6 wherein the signal sequencing of the resettable CTIA and the in-pixel CDS circuit further comprises:

resetting the resettable CTIA by momentarily closing the loop-reset switch;

transferring a sampled reset signal from the output terminal onto the reset signal storage capacitor of the reset sampling branch using a corresponding setting of the plurality of reset multiplexing switches;

transferring and converting the accumulated charge signal on the photodiode cathode into the outbound photoelectric signal at the output terminal by momentarily closing the transfer control switch; and

transferring a sampled image signal from the output terminal onto the image signal storage capacitor of the image sampling branch using a corresponding setting of the plurality of image multiplexing switches

whereby allows the desired output video signal, being the difference between the sampled image signal and the sampled reset signal, to be substantially free of noise distortion by a Reset kTC noise generated with each closure of the loop-reset switch.

8. The high image quality pixel readout circuitry of claim 6 wherein both the image signal storage capacitance and the reset signal storage capacitance are selected to be much bigger than the charge integration capacitance whereby further minimize the image-degrading effect of inter-pixel differential leakage of the charge signal through the operational amplifier thus further improving the snapshot operation mode.

9. An in-pixel correlated multiple sampling (CMS) circuitry for converting an input photoelectric signal, generated by a switch-resettable photoelectric conversion amplifier in response to an incoming image light pixel, into a corresponding output video signal, the in-pixel CMS circuitry comprises a serial connection of:

a) an input end being connected to the input photoelectric signal;

b) a following parallel connection of;

a switched image sampling branch having an image signal storage capacitor and a plurality of image multiplexing switches for providing a sampled image signal corresponding to said input photoelectric signal; and

a plurality of switched reset sampling branches (RSB₁, RSB₂, . . . , RSB_j, . . . , RSB_N) where N>

=2 with each RSB_j further comprises;

a reset signal storage capacitor RSC_j and a plurality of reset multiplexing switches MSW_j for providing a sampled reset signal corresponding to a reset voltage at the output of the switch-resettable photoelectric conversion amplifier upon its reset;

c) a following difference amplifier attached to the parallel connection; and

d) wherein said image multiplexing switches and said reset multiplexing switches MSW_j are further sequenced so as to result in a delivery of the following cyclic sequence of signal pairs to the difference amplifier;

(sampled image signal, sampled reset signal from RSB₁), (sampled image signal, sampled reset signal from RSB₂), . . . , (sampled image signal, sampled reset signal from RSB_j), . . . , (sampled image signal, sampled reset signal from RSB_N)

whereby allows the output video signal, being produced by the difference amplifier as the difference between the sampled image signal and the plurality of sampled reset signal from RSB_j, to be substantially free of noise distortion by a Reset kTC noise accompanying the reset voltage.

10. The in-pixel CMS circuitry of claim 9 where the switch-resettable photoelectric conversion amplifier is a resettable unity gain amplifier (UGA).

11. The in-pixel CMS circuitry of claim 9 where the switch-resettable photoelectric conversion amplifier is a resettable capacitive trans-impedance amplifier (CTIA).

12. The in-pixel CMS circuitry of claim 11 where the resettable CTIA further comprises a transfer control switch bridging a photodiode cathode and a negative input terminal within the resettable CTIA.

13. The in-pixel CMS circuitry of claim 9 wherein N=2 thus the sequencing of said image multiplexing switches and said reset multiplexing switches MSW_j result in a toggled delivery between the following two signal pairs to the difference amplifier:

(sampled image signal, sampled reset signal from RSB₁), (sampled image signal, sampled reset signal from RSB₂).