SYSTEM AND METHOD FOR ON-BOARD DIAGNOSTICS OF MEMORY MODULES

• US 20090106591A1
• Filed: 12/30/2008
• Published: 04/23/2009
• Est. Priority Date: 08/19/2003
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Granted Patent: US 7,913,122 B2
• Time in Patent Office: Days
• US Class Current: 714/31
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
• CPC Class Codes: G11C 29/56004 Pattern generation
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a memory device interface coupled to the memory devices for coupling memory requests to the memory devices. A memory hub diagnostic engine is coupled through a switch to the link interface and the memory device interface to perform diagnostic testing of the memory system. The diagnostic engine includes a maintenance port that provides access to results of the diagnostic testing and through which diagnostic testing commands can be received.

Claims

1-32. -32. (canceled)

33. A system comprising:

a plurality of memory systems, each of the memory systems including a respective plurality of memory devices and logic coupled to the memory devices, the logic comprising;

a memory device interface configured to provide signals to the memory devices receive signals from the memory devices; and

a diagnostic test engine coupled to the memory device interface and configured to receive diagnostic testing commands and monitor memory system operation while at least one of the memory devices is operating.

34. The system of claim 33 wherein the diagnostic test engine is configured to monitor control, address, or data signals, or combinations thereof while at least one of the memory devices is operating.

35. The system of claim 33 wherein the diagnostic test engine is further configured to provide diagnostic testing results based in part on the monitoring.

36. The system of claim 33 wherein the monitoring memory system operation includes monitoring signals transmitted to or received from the memory devices, or both.

37. The system of claim 33 wherein the diagnostic engine comprises:

a maintenance port interface configured to translate the diagnostic testing commands into control signals for the diagnostic test engine;

a pattern generator coupled to the maintenance port interface and configured to generate test patterns for diagnostic testing of the memory devices in response to receiving control signals from the maintenance port interface;

a sequencer coupled to the maintenance port interface configured to access the memory devices, the sequencer generating memory commands based on the control signals received from the maintenance port interface; and

a memory device interface controller coupled to the maintenance port and further coupled to the memory device interface, the memory device interface controller configured to monitor the transmission of signals to the memory devices and reception of data signals from the memory devices.

38. The system of claim 37 wherein the memory device interface controller is configured to monitor the transmission of control, address, or write data signals, or combinations thereof and monitor the reception of read data signals from the memory devices.

39. The system of claim 33 wherein the diagnostic test engine is configured to monitor signal timing, voltage margin, or both of signals sent to the memory devices.

40. The system of claim 33 wherein the diagnostic test engine is configured to control transmission and reception of signals by the memory device interface.

41. The system of claim 40 wherein the memory device interface includes transmitter and receiver logic and wherein the diagnostic test engine is configured to control at least one of drive strength and slew rate of the transmitter logic, and filter coefficients of the receiver logic.

42. The system of claim 33 wherein the logic further comprises a direct memory access (DMA) engine coupled to the diagnostic test engine, the DMA engine operable to retrieve and load data patterns for testing into the logic.

43. The system of claim 33 wherein the DMA engine is configured to store signal trace history for at least one of the signals sent to the memory devices for retrieval through the host computer system interface.

44. A system comprising:

a plurality of memory systems coupled to a link on which signals are transmitted, each of the memory systems including;

a plurality of memory devices and logic coupled to the memory devices, the logic comprising;

a plurality of link interfaces coupled to the link, the link interfaces configured to transmit and receive control, address and data signals on the link; and

a diagnostic test engine coupled to the link interface and configured to receive diagnostic testing commands and provide diagnostic testing results, the diagnostic test engine configured to monitor memory system operation and provide results from monitoring the memory system operation to a host computer system as diagnostic testing results.

45. The system of claim 44 wherein the diagnostic test engine is configured to monitor memory system operation while signals are transmitted or received on the link.

46. The system of claim 44 wherein the diagnostic test engine is configured to monitor control, address, data signals, or combinations thereof while signals are transmitted or received on the link.

47. The system of claim 44 wherein the diagnostic test engine is configured to receive the diagnostic testing commands from the host computer system.

48. The system of claim 44 wherein the diagnostic engine comprises:

a maintenance port interface configured to translate the diagnostic testing commands into control signals for the diagnostic test engine;

a pattern generator coupled to the maintenance port interface and configured to generate test patterns for diagnostic testing of the memory devices in response to receiving control signals from the maintenance port interface;

a sequencer coupled to the maintenance port interface configured to access the memory devices, the sequencer generating memory commands based on the control signals received from the maintenance port interface; and

a link interface controller coupled to the maintenance port and further coupled to the link interface, the link interface controller configured to monitor the transmission of at least one of control, address, and data signals on the link.

49. The system of claim 44 wherein the diagnostic test engine is configured to monitor signal timing, voltage margin, or both of the control, address, or data signals, or combinations thereof.

50. The system of claim 44 wherein the diagnostic test engine is configured to control transmission and reception of signals by at least one of the link interfaces.

51. The system of claim 50 wherein the link interfaces include transmitter and receiver logic and wherein the diagnostic test engine is configured to control drive strength, slew rate, or both of the transmitter logic, or filter coefficients of the receiver logic, or combinations thereof.

52. The system of claim 44 wherein the logic further comprises a direct memory access (DMA) engine coupled to the diagnostic test engine, the DMA engine operable to retrieve and load data patterns for testing into the logic.

53. The system of claim 52 wherein the DMA engine is further configured to store signal trace history for monitored memory system operation for retrieval through the host computer system interface.

54. A method for evaluating performance of a memory system having a plurality of memory devices coupled to logic including a diagnostic engine, the method comprising:

receiving diagnostic testing commands at the diagnostic engine;

controlling a link interface circuit to monitor signals transmitted or received on a link to which the logic is coupled;

controlling a memory device interface circuit to monitor signals during transmission to or reception of the respective signals from the memory devices;

storing the results of monitoring by the memory device interface circuit and the results of monitoring by the link interface circuits in a memory; and

providing diagnostic testing commands to the diagnostic engine to retrieve the stored results and provide the same over a maintenance port of the diagnostic engine.

55. The method of claim 54 wherein the controlling the link interface circuit includes controlling the link interface circuit to monitor control, address, or data signals, or combinations thereof.

56. The method of claim 55 wherein controlling the link interface circuit to monitor control, address, or data signals, or combinations thereof transmitted or received on a link to which the memory hub of the memory module is coupled comprises controlling the link interface circuits to monitor signal timing, voltage margin, or both the control, address, or data signals, or combinations thereof.

57. The method of claim 55 wherein controlling the link interface circuit to monitor control, address, or data signals, or combinations thereof, transmitted or received on a link to which the logic is coupled comprises controlling drive strength, slew rate, or both of transmitter logic of the link interface, or filter coefficients of receiver logic of the link interface, or combinations thereof.

58. The method of claim 54 wherein the controlling the memory device interface circuit includes controlling the memory device interface circuit to monitor control, address, write data signals, or read data signals, or combinations thereof.

59. The method of claim 58 wherein controlling the memory device interface circuit to monitor control, address, write data signals, or read data signals, or combinations thereof during transmission to or reception of the respective signals from the memory devices comprises controlling the memory device interface circuit to monitor signal timing, voltage margin, or both of the control, address, write data signals, or read data signals, or combinations thereof.

60. The method of claim 58 wherein controlling the memory device interface circuit to monitor control, address, write data signals, or read data signals, or combinations thereof during transmission to or reception of the respective signals from the memory devices comprises controlling at drive strength, slew rate, or both of transmitter logic of the memory device interface, or filter coefficients of receiver logic of the memory device interface, or combinations thereof.