SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE

• US 20090108342A1
• Filed: 10/31/2007
• Published: 04/30/2009
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Grivna, Gordon M., Wang, Hui, Nemtsev, Gennadiy, Zheng, Yingping
• Granted Patent: US 8,207,037 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A semiconductor component that includes a field plate and a semiconductor device and a method of manufacturing the semiconductor component. A semiconductor material includes an epitaxial layer disposed on a semiconductor substrate. A trench having an upper portion and a lower portion is formed in the epitaxial layer. A portion of a field plate is formed in the lower portion of the trench, wherein the field plate is electrically isolated from trench sidewalls. A gate structure is formed in the upper portion of the trench, wherein a gate oxide is formed from opposing sidewalls of the trench. Gate electrodes are formed adjacent to the gate oxide formed from the opposing sidewalls and a dielectric material is formed adjacent to the gate electrode. Another portion of the field plate is formed in the upper portion of the trench and cooperates with the portion of the field plate formed in the lower portion of the trench to form the field plate.

Claims

1. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor material having first and second opposing surfaces;

forming at least one trench in the semiconductor material, the at least one trench having at least one sidewall;

forming a dielectric material in the at least one trench;

forming a semiconductor material in the at least one trench, the dielectric material between the semiconductor material and the at least one sidewall of the at least one trench;

forming a portion of a gate structure within the at least one trench; and

forming additional semiconductor material within the at least one trench, the additional semiconductor material electrically separated from the portion of the gate structure.

2. The method of claim 1, wherein the at least one sidewall comprises first and second sidewalls, and wherein forming the dielectric material in the at least one trench includes forming a first portion of the dielectric material adjacent the first sidewall and forming a second portion of the dielectric material adjacent the second sidewall, and forming the semiconductor material in the at least one trench includes forming the semiconductor material between first and second portions of the dielectric material.

3. The method of claim 2, further including:

removing a portion of the semiconductor material between the first and second portions of the dielectric material to form a first electrically conductive structure; and

removing subportions of the first and second portions of the dielectric material.

4. The method of claim 3, further including:

forming dielectric material from portions of the first and second sidewalls of the at least one trench; and

forming a gate electrode adjacent the dielectric material formed from the first and second sidewalls of the at least one trench.

5. The method of claim 4, wherein forming the dielectric material includes oxidizing portions of the semiconductor material exposed by the at least one trench and wherein forming the gate electrode includes depositing an electrically conductive material adjacent the dielectric material formed from the portions of the first and second sidewalls of the at least one trench.

6. The method of claim 5, further including forming a layer of dielectric material over the electrically conductive material and removing portions of the layer of dielectric material to form first and second dielectric barriers that are laterally spaced apart from the first and second sidewalls of the at least one trench, wherein the first and second dielectric barriers have first and second sides, and removing a portion of the electrically conductive material between the first side of the first dielectric barrier and the first sidewall and removing a portion of the electrically conductive material between the first side of the second dielectric barrier and the second sidewall.

7. The method of claim 6, wherein the electrically conductive material comprises one of a doped layer of polysilicon or multi-layer structure comprising a silicide between first and second doped layers of polysilicon.

8. The method of claim 6, further including:

forming a first dielectric material between the first dielectric barrier and the first sidewall;

forming a second dielectric material between the second dielectric barrier and the second sidewall;

forming a third dielectric material laterally adjacent the second side of the first dielectric barrier; and

forming a fourth dielectric material laterally adjacent the second side of the second dielectric barrier.

9. The method of claim 8, further including forming an electrically conductive plug between the second sides of the first and second dielectric barriers and over the electrically conductive structure.

10. The method of claim 9, further including forming a doped region in a portion of the semiconductor material adjacent the first surface.

11. The method of claim 9, further including forming a contact structure to the electrically conductive plug.

12. A method for manufacturing a semiconductor component, comprising:

providing a semiconductor substrate of a first conductivity type;

forming an epitaxial layer of the first conductivity type and a first resistivity over the semiconductor substrate, the epitaxial layer having a major surface;

forming a trench in the epitaxial layer, the trench having first and second sidewalls and a second trench region over a first trench region;

forming a field plate in the first trench region;

forming a gate dielectric adjacent the first sidewall in the second trench region;

forming a gate electrode in the second trench region, the gate electrode adjacent the gate dielectric;

forming a dielectric material adjacent the gate electrode; and

forming a conductive plug in the second trench region, the conductive plug electrically coupled to the field plate and electrically isolated from the gate electrode.

13. The method of claim 12, wherein forming the field plate in the first region includes forming a dielectric material adjacent the first and second sidewalls and forming the field plate adjacent the dielectric material, wherein the dielectric material electrically isolates the field plate from the first and second sidewalls.

14. The method of claim 13, further including forming a doped region in the epitaxial layer, the doped region extending from the surface into the epitaxial layer a distance that is less than a distance the trench extends into the epitaxial layer.

15. The method of claim 14, further including forming a gate connect structure over the epitaxial layer.

16. The method of claim 15, wherein the gate connect structure comprises one of a layer of doped polysilicon or a multi-layer structure having a silicide layer between a plurality of doped polysilicon layers.

17. The method of claim 14, further including:

forming a layer of dielectric material over the epitaxial layer and the trench;

forming an opening in the layer of dielectric material that is over the epitaxial layer to expose the conductive plug in the second trench region; and

forming a contact to the conductive plug in the second trench region.

18. A semiconductor component, comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer of the first conductivity type and a first resistivity over the semiconductor substrate, the epitaxial layer having a major surface;

a trench extending from the major surface into the epitaxial layer, the trench having first and second sidewalls;

an electrically conductive material within a first portion of the trench, the electrically conductive material spaced apart from the first and second sidewalls by a dielectric material;

a gate oxide adjacent the first and second sidewalls of a second portion of the trench;

a gate electrode adjacent the gate oxide;

dielectric spacers within a second portion of the trench, the dielectric spacers adjacent the gate electrode; and

additional electrically conductive material within the second portion of the trench, the additional electrically conductive material spaced apart from the gate electrode by the dielectric spacers.

19. The semiconductor component of claim 18, further including:

a gate contact over a portion of the epitaxial layer; and

a contact structure electrically coupled to the additional electrically conductive material and the epitaxial layer.

20. The semiconductor component of claim 18, wherein the dielectric material separating the electrically conductive material from the first sidewall has a thickness of at least about 7,500 Angstroms and the dielectric material separating the electrically conductive material from the second sidewall has a thickness of at least about 7,500 Angstroms.