PHASE-CHANGE MEMORY DEVICE WITH ERROR CORRECTION CAPABILITY

• US 20090109738A1
• Filed: 09/12/2008
• Published: 04/30/2009
• Est. Priority Date: 09/13/2007
• Status: Active Grant

• Current Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Bedeschi, Ferdinando, Donze, Enzo Michele, Jagasivamani, Meenatchi
• Granted Patent: US 7,869,269 B2
• Time in Patent Office: Days
• US Class Current: 365/163
• CPC Class Codes: B01F 27/1121 pin-shaped
• CPC Class Codes: B01F 27/1144 with a plurality of blades following a helical path on a shaft or a blade support
• CPC Class Codes: B01F 27/70 with paddles, blades or arms
• CPC Class Codes: B01F 33/70 Mixers specially adapted for working at sub- or super-atmospheric pressure, e.g. combined with de-foaming
• CPC Class Codes: B01F 35/715 Feeding the components in several steps, e.g. successive steps
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 13/02 using elements whose operation depends upon chemical change G11C13/0009 takes precedence

Abstract

A phase-change memory device includes a plurality of data PCM cells for storing data bits; data decoding circuits for selectively addressing sets of data PCM cells; and data read/program circuits for reading and programming the selected data PCM cells. The device further includes a plurality of parity PCM cells for storing parity bits associated with data bits stored in the data PCM cells; parity decoding circuits for selectively addressing sets of parity PCM cells; and parity read/program circuits for reading and programming the selected parity PCM cells.

Claims

1. A phase-change memory device, comprising:

a plurality of data PCM cells configured to store data bits;

data decoding circuits structured to selectively address sets of the data PCM cells;

data read/program circuits configured to read and program the sets of the data PCM cells;

a plurality of parity PCM cells configured to store parity bits associated with data bits stored in the data PCM cells;

parity decoding circuits configured to selectively address sets of the parity PCM cells; and

parity read/program circuits configured to read and program the sets of the parity PCM cells.

2. A device according to claim 1 wherein the data PCM cells and the parity PCM cells are organized in a plurality of tiles and each tile includes:

one of the sets of the data PCM cells;

one of the sets of the parity PCM cells;

a plurality of local word lines coupled to the set of data PCM cells and the set of parity PCM cells of the tile;

a plurality of data bit lines with data PCM cells connected thereto; and

a plurality of parity bit lines with parity PCM cells connected thereto.

3. A device according to claim 2 wherein the tiles are further organized in a plurality of elementary building blocks and each elementary building block comprises two respective adjacent tiles.

4. A device according to claim 3 wherein the elementary building blocks each comprise:

a respective one of the parity read/program circuits, wherein each parity read/program circuit is associated with parity bit lines of both tiles of the respective elementary building block; and

a respective one of the parity decoding circuits, wherein each parity decoding circuit is configured to address parity bit lines of both tiles of the respective elementary building block and to connect selected parity bit lines to the respective parity read/program circuit of the respective elementary building block.

5. A device according to claim 3 wherein all the elementary building blocks have identical electrical structure.

6. A device according to claim 3 wherein each elementary building block further includes a plural number of data read/program circuits for each tile of the elementary building block and the data read/program circuits of the elementary building block are respectively associated with respective groups of data bit lines of the respective tile.

7. A device according to claim 6 wherein parity bit lines associated with each tile are half as many as the data bit lines in each group of the tile.

8. A device according to claim 3 wherein the elementary building blocks further include respective local word line decoding portions of the data decoding circuits and of the parity decoding circuits.

9. A device according to claim 3 wherein the set of parity PCM cells of each tile of each elementary building block is arranged between the set of data PCM cells of the tile and the other tile of the elementary building block.

10. A device according to claim 3 wherein the elementary building blocks are further organized in a plurality of partitions, each partition including a plurality of planes, and each plane including a plurality of the elementary building blocks.

11. A device according to claim 1, comprising an error correction module coupled to the data and parity read/program circuits.

12. A system, comprising:

a processing unit;

an interface coupled to the processing unit; and

a phase-change memory device coupled to the processing unit, the memory device including;

a plurality of data PCM cells configured to store data bits;

data decoding circuits structured to selectively address sets of the data PCM cells;

data read/program circuits configured to read and program the sets of the data PCM cells;

a plurality of parity PCM cells configured to store parity bits associated with data bits stored in the data PCM cells;

parity decoding circuits configured to selectively address sets of the parity PCM cells; and

parity read/program circuits configured to read and program the sets of the parity PCM cells.

13. A system according to claim 12 wherein the data PCM cells and the parity PCM cells are organized in a plurality of tiles and each tile includes:

one of the sets of the data PCM cells;

one of the sets of the parity PCM cells;

a plurality of local word lines coupled to the set of data PCM cells and the set of parity PCM cells of the tile;

a plurality of data bit lines with data PCM cells connected thereto; and

a plurality of parity bit lines with parity PCM cells connected thereto.

14. A system according to claim 13 wherein the tiles are further organized in a plurality of elementary building blocks and each elementary building block comprises two respective adjacent tiles.

15. A system according to claim 14 wherein the elementary building blocks each comprise:

a respective one of the parity read/program circuits, wherein each parity read/program circuit is associated with parity bit lines of both tiles of the respective elementary building block; and

a respective one of the parity decoding circuits, wherein each parity decoding circuit is configured to address parity bit lines of both tiles of the respective elementary building block and to connect selected parity bit lines to the respective parity read/program circuit of the respective elementary building block.

16. A system according to claim 14 wherein each elementary building block further includes a plural number of data read/program circuits for each tile of the elementary building block and the data read/program circuits of the elementary building block are respectively associated with respective groups of data bit lines of the respective tile.

17. A system according to claim 14 wherein the elementary building blocks further include respective local word line decoding portions of the data decoding circuits and of the parity decoding circuits.

18. A system according to claim 14 wherein the set of parity PCM cells of each tile of each elementary building block is arranged between the set of data PCM cells of the tile and the other tile of the elementary building block.

19. A system according to claim 14 wherein the elementary building blocks are further organized in a plurality of partitions, each partition including a plurality of planes, and each plane including a plurality of the elementary building blocks.

20. A phase-change memory device, comprising:

a plurality of elementary building blocks each including;

respective first and second tiles, each tile including;

a plurality of sets of data PCM cells configured to store data bits;

a plurality of data decoding circuits coupled respectively to the sets of data PCM cells of the tile, each data decoding circuit being structured to selectively address the respective set of data PCM cells;

data read/program circuits configured to read and program the sets of data PCM cells of the tile, respectively; and

a set of parity PCM cells configured to store parity bits associated with data bits stored in the data PCM cells;

a parity decoding circuit configured to selectively address the sets of parity PCM cells of both tiles of the elementary building block; and

a parity read/program circuit configured to read and program the sets of parity PCM cells of both tiles of the elementary building block.

21. A device according to claim 20 wherein each tile includes:

a local row decoder; and

a plurality of local word lines coupling the local row decoder to the sets of data PCM cells and the set of parity PCM cells of the tile.

22. A device according to claim 20 wherein the set of parity PCM cells of each tile of each elementary building block is arranged between the set of data PCM cells of the tile and the other tile of the elementary building block.

23. A device according to claim 20 wherein the elementary building blocks are further organized in a plurality of partitions, each partition including a plurality of planes, and each plane including a plurality of the elementary building blocks.

24. A device according to claim 20, comprising an error correction module coupled to the data and parity read/program circuits.