HIGH-MOBILITY TRENCH MOSFETS

• US 20090114949A1
• Filed: 11/01/2007
• Published: 05/07/2009
• Est. Priority Date: 11/01/2007
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Hebert, Francois
• Granted Patent: US 7,994,005 B2
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

High-mobility vertical trench DMOSFETs and methods for manufacturing are disclosed. A source region, a drain region or a channel region of a high-mobility vertical trench DMOSFET may comprise silicon germanium (SiGe) that increases the mobility of the charge carriers in the channel region. In some embodiments the channel region may be strained to increase channel charge carriers mobility.

Claims

1. A high-mobility vertical trench DMOS, comprising:

a trenched gate;

a top source region disposed next to the trenched gate;

a bottom drain region disposed below the bottom of the trenched gate; and

a channel region proximate to a sidewall of the trenched gate between the source and drain regions

wherein at least one of the channel region, source region and drain region comprises SiGe configured to increase the mobility of charge carriers in the channel region.

2. A high-mobility vertical trench DMOS, comprising:

a trenched gate;

a top source region disposed next to the trenched gate;

a bottom drain region disposed below the bottom of the trenched gate; and

a channel region proximate to a sidewall of the trenched gate between the source and drain regions;

wherein the channel region is strained to increase channel charge carriers mobility.

3. The high-mobility vertical trench DMOS of claim 2 wherein the channel region comprises SiGe.

4. The high-mobility vertical trench DMOS of claim 3 wherein the channel region includes P-type SiGe.

5. The high-mobility vertical trench DMOS of claim 4, wherein the drain region comprises SiGe.

6. The high-mobility vertical trench DMOS of claim 5, wherein the drain region includes N-type SiGe.

7. The high-mobility vertical trench DMOS of claim 2, wherein the source region comprises SiGe.

8. The high-mobility vertical trench DMOS of claim 7, wherein the source region includes an N+ strained SiGe source.

9. The high-mobility vertical trench DMOS of claim 8, wherein the drain region comprises SiGe.

10. The high-mobility vertical trench DMOS of claim 9, wherein the drain region includes N-type SiGe.

11. A method for manufacturing a high-mobility vertical trenched DMOS comprising:

a) forming an N-type epitaxial (N-epi) layer on top of the N+ substrate;

b) forming a trench mask on top of the N-epi layer;

c) etching the N-epi layer through the trench mask to a predetermined depth to form a trench;

d) filing the trench with a conductive material to form a gate; and

e) forming SiGe region proximate to the gate, wherein the SiGe region configured to increase a mobility of charge carriers in a channel region.

12. The method of claim 11 wherein step e) is performed before step d).

13. The method of claim 11 further comprising forming a P-body layer on the surface of the N-epi layer

14. The method of claim 13, wherein step e) comprises:

depositing an undoped SiGe layer with a predetermined depth on a sidewall and a bottom of the trench;

implanting N-type dopants in the deposited undoped SiGe portion at the bottom of the trench; and

annealing the deposited SiGe layer.

15. The method of claim 14 further comprising forming a gate oxide layer on the gate between step d) and step e).

16. The method of claim 13, wherein step e) comprises:

growing a thin oxide layer in the trench;

forming a nitride layer over the thin oxide layer;

partially etching the nitride layer to form nitride spacer;

etching a portion of the thin oxide layer at a bottom of the trench;

etching at least a portion of the N-epi layer to a predetermined depth;

forming a thick oxide layer on the portion of the N-epi layer that was etched;

removing the nitride spacer and thin oxide layer from a sidewall of the trench;

growing P-type SiGe on the sidewall of the trench;

etching back the thick oxide layer; and

forming a gate oxidation layer on the P-type SiGe on the sidewall of the trench.

17. The method of claim 13, wherein step e) comprises:

forming an oxide spacer on the trench sidewall;

isotropically etching a portion of the N-epi layer at a bottom of the trench;

selectively growing an N-type SiGe region on the portion of the N-epi layer that was isotropically etched;

etching the oxide spacer and the trench mask; and

forming a gate oxide layer on the N-type SiGe on the sidewall of the trench.

18. The method of claim 13, wherein step e) comprises:

depositing undoped SiGe into the trench;

forming an oxide layer on top of the undoped SiGe layer;

etching back the oxide layer at a bottom of the trench to expose a portion of the undoped SiGe and to form an oxide spacer on a sidewall of the trench;

etching a portion of the undoped SiGe layer at the bottom of the trench to expose an underlying portion of the N-epi layer;

isotropically etching the undoped SiGe layer and the N-epi layer at the bottom of the trench;

removing the oxide spacer from the sidewall; and

forming a gate oxide in the trench over the bottom of the trench and over the undoped SiGe layer on the sidewall of the trench.

19. The method of claim 11 wherein step d) is performed before step e).

20. The method of claim 19 further comprising, before step d):

removing the trench mask; and

forming a gate oxide on the gate.

21. The method of claim 20, further comprising:

after step e);

implanting and diffusing the top region of the N-epi layer to form P-body layer; and

forming a poly oxide layer on top of the gate; and

etching the oxide layer on top of the P-body layer.

22. The method of claim 21, wherein step e) comprises:

selectively growing N+ SiGe region on top of the P-body layer; and

etching back the N+ SiGe region to a predetermined width to form a source region.

23. The method of claim 19 further comprising forming a gate oxide before step d).

24. The method of claim 23 further comprising after step d):

implanting and diffusing a top region of the N-epi layer to form a P-body layer;

removing the trench mask; and

forming an oxide layer over the gate.

25. The method of claim 24, wherein step e) comprises:

selectively growing N+ SiGe region on top of the P-body layer; and

etching back the N+ SiGe region to a predetermined width to form a source region.