Architectural Enhancements to CPU Microde Load Mechanism for Information Handling Systems

• US 20090119495A1
• Filed: 11/05/2007
• Published: 05/07/2009
• Est. Priority Date: 11/05/2007
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Khatri, Mukund
• Granted Patent: US 7,882,333 B2
• Time in Patent Office: Days
• US Class Current: 712/245
• CPC Class Codes: G06F 9/4403 Processor initialisation

Abstract

A method for loading microcode to a plurality of cores within a processor. The method includes loading the microcode to a first core of the plurality of cores within the processor system and generating a broadcast inter process interrupt (IPI) message via the first core. The IPI message causes other cores within the processor system to synchronize respective microcode with the microcode that is loaded into the first core. The synchronizing loads microcode to the plurality of cores without requiring independent loads of microcode to each core.

Claims

1. A method for loading microcode to a plurality of cores within a processor system comprising

loading the microcode to a first core of the plurality of cores within the processor system;

generating a broadcast inter processor interrupt (IPI) message via the first core, the IPI message causing other cores within the processor system to synchronize respective microcode with the microcode that is loaded into the first core, the synchronizing loading microcode to the plurality of cores without requiring independent loads of microcode to each core.

2. The method of claim 1, further comprising:

determining whether an additional processor is present within the processor system, where the additional processor comprises a plurality of processor cores; and

, if an additional processor is present, then

loading the microcode to a first core of the additional processor; and

,

generating a broadcast IPI message via the first core of the additional processor.

3. The method of claim 1, wherein:

the first core of the plurality of cores comprises a boot strap processor (BSP) core.

4. The method of claim 1, wherein:

the other cores of the plurality of cores comprise application processor (AP) cores.

5. The method of claim 1, further comprising:

synchronizing machine specific register (MSR) information, and memory type range register (MTRR) information via the broadcast IPI message.

6. An apparatus method for loading microcode to a plurality of cores within a processor system comprising

means for loading the microcode to a first core of the plurality of cores within the processor system;

means for generating a broadcast inter processor interrupt (IPI) message via the first core, the IPI message causing other cores within the processor system to synchronize respective microcode with the microcode that is loaded into the first core, the synchronizing loading microcode to the plurality of cores without requiring independent loads of microcode to each core.

7. The apparatus of claim 6, further comprising:

means for determining whether an additional processor is are present within the processor system, where the additional processor comprises a plurality of processor cores; and

, if an additional processor is present, then

means for loading the microcode to a first core of the additional processor; and

,

means for generating a broadcast IPI message via the first core of the additional processor.

8. The apparatus of claim 6, wherein:

the first core of the plurality of cores comprises a boot strap processor (BSP) core.

9. The apparatus of claim 6, wherein:

the other cores of the plurality of cores comprise application processor (AP) cores.

10. The apparatus of claim 6, further comprising:

means for synchronizing machine specific register (MSR) information and memory type range register (MTRR) information via the broadcast IPI message.

11. An information handling system comprising

a processor system, the processor system comprising a plurality of processor cores;

and,

a memory coupled to the processor system, the memory storing a microcode load module for loading microcode to the plurality of cores within a processor system, the microcode load module comprising instructions for;

loading the microcode to a first core of the plurality of cores within the processor system;

generating a broadcast inter processor interrupt (IPI) message via the first core, the IPI message causing other cores within the processor system to synchronize respective microcode with the microcode that is loaded into the first core, the synchronizing loading microcode to the plurality of cores without requiring independent loads of microcode to each core.

12. The information handling system of claim 11 wherein the microcode load module further comprises instructions for:

determining whether an additional processors is present within the processor system, where the additional processor comprises a plurality of processor cores; and

, if an additional processor is present, then

loading the microcode to a first core of the additional processor; and

,

generating a broadcast IPI message via the first core of the additional processor.

13. The information handling system of claim 11, wherein:

the first core of the plurality of cores comprises a boot strap processor (BSP) core.

14. The information handling system of claim 11, wherein:

the other cores of the plurality of cores comprise application processor (AP) cores.

15. The information handling system of claim 11, wherein the instructions further comprise instructions for:

synchronizing machine specific register (MSR) information, and memory type range register (MTRR) information via the broadcast IPI message.