METHODS AND APPARATUS FOR SIGNALING ON A DIFFERENTIAL LINK

• US 20090122905A1
• Filed: 01/14/2009
• Published: 05/14/2009
• Est. Priority Date: 03/14/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Schoenborn, Zale T.
• Granted Patent: US 8,908,807 B2
• Time in Patent Office: Days
• US Class Current: 375/286
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/4917 using multilevel codes

Abstract

Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.

Claims

1. A receiver for use with a differential serial data link including at least two lines, the receiver comprising:

a difference detector to develop an output signal representative of a voltage difference between the at least two lines;

an integrator to integrate the output signal to develop an integrated signal;

a signaling circuit to signal a first portion of the receiver when the integrated signal exceeds a threshold; and

a second signaling circuit to signal a second portion of the receiver when the integrated voltage exceeds a second threshold which is higher than the first threshold;

wherein the integrated voltage exceeds the second threshold when a first difference signal and a second difference signal are received in succession via the differential serial data link.

2. A receiver as defined in claim 1 wherein the integrator comprises an RC circuit.

3. A receiver as defined in claim 1 further comprising an AC coupling circuit associated with the differential serial data link and including at least two AC coupling capacitors and at least two shunt impedances;

the AC coupling capacitors, the shunt impedances, and the RC circuit of the integrator being dimensioned such that the AC coupling circuit passes a signal sufficient to develop an integrated signal exceeding the first threshold in response to a first DC difference signal of a first predetermined duration and a first predetermined magnitude being received via the differential serial data link at the AC coupling circuit.

4. A receiver as defined in claim 3 wherein the integrated voltage exceeds the second threshold when both the first DC difference signal and a second DC difference signal are received in succession by the AC coupling circuit.

5. A receiver as defined in claim 1 wherein the at least a first portion of the receiver is responsive to the signal from the signaling circuit to transition from a first state to a second state.

6. A receiver as defined in claim 5 wherein the first state is a reduced power state and the second state is a normal power state.

7. A receiver as defined in claim 5 wherein the first state is a reduced power state and the second state is a reset state.

8. A receiver as defined in claim 5 wherein the first state is a reduced power state and the second state is a reduced power state wherein the receiver relays an in-band signal to a second receiver via a second differential serial data link.

9. A receiver as defined in claim 1 wherein the voltage difference is a DC common mode shift.

10. A receiver as defined in claim 1 wherein the difference detector comprises an operational amplifier.

11. A receiver as defined in claim 10 wherein the operational amplifier has low gain.

12. A receiver as defined in claim 10 further comprising a rectifier to rectify the output signal of the operational amplifier prior to integration.