Spatial light modulator and mirror array device
First Claim
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1. A spatial light modulator, comprising:
- a pixel array comprises a plurality of pixel units;
each of the pixel units further comprises a memory cell;
a plurality of word lines and a plurality of plate lines for electrically communicating with the pixel units; and
a plurality of bit line sets wherein each of the sets includes a pair of bit lines each connected to a memory cell, wherein at least one pair of the memory cells connected to the pair of bit lines are on a same row connected to a same word line.
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Abstract
The present invention provides a spatial light modulator, comprising: a pixel array comprises a plurality of pixel units. Each of the pixel units comprises a memory cell. A plurality of word lines and a plurality of plate lines to electrically communicate with the pixel units. A plurality of bit line sets wherein each of the sets includes a pair of bit lines each connected to a memory cell, wherein at least one pair of the memory cells connected to the pair of bit lines are on a same row connected to a same word line.
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12 Claims
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1. A spatial light modulator, comprising:
a pixel array comprises a plurality of pixel units;
each of the pixel units further comprises a memory cell;
a plurality of word lines and a plurality of plate lines for electrically communicating with the pixel units; and
a plurality of bit line sets wherein each of the sets includes a pair of bit lines each connected to a memory cell, wherein at least one pair of the memory cells connected to the pair of bit lines are on a same row connected to a same word line.- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 11)
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10. A spatial light modulator, comprising:
a pixel array comprises a plurality of pixel units;
each of the pixel units comprises a memory cell for retaining data applied for driving the pixel unit;
a plurality of word lines and a plurality of plate lines for electrically communicating with the pixel units; and
a plurality of bit lines for transmitting the data to the memory cell, wherein the memory comprises a transistor and a capacitor, a word line is connected to the gate of the transistor, the first plate of the capacitor is connected to a source of the transistor to for connecting to the bit line, the second plate of the capacitor is connected to the plate line, a plurality of bit line sets wherein each of the sets includes two of the bit lines, and the plate line is connected to at least one of two of the memory cells connected to the set of bit lines wherein the memory cell are disposed on one row in a direction along the word line of the pixel array.- View Dependent Claims (12)
Specification