Data Cache Architecture and Cache Algorithm Used Therein

• US 20090132770A1
• Filed: 11/20/2007
• Published: 05/21/2009
• Est. Priority Date: 11/20/2007
• Status: Active Grant

• Current Assignee: Solid State System Co., Ltd.
• Original Assignee: Solid State System Co., Ltd.
• Inventors: Lin, Yen-Chin
• Granted Patent: US 7,814,276 B2
• Time in Patent Office: Days
• US Class Current: 711/154
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0886 Variable-length word access
• CPC Class Codes: G06F 2212/2022 Flash memory

Abstract

The present invention provides a data cache architecture interposed between a host and a flash memory, the data cache architecture comprising: a buffer memory, receiving data from the host; a memory controller, deploying the data in the buffer memory; and a data cache memory, controlled by the memory controller according to a cache algorithm. The data cache architecture and the cache algorithm used in the data cache architecture can be used to minimize the program/erase count of the NAND type flash device.

Claims

1. A data cache architecture interposed between a host and a flash memory, the data cache architecture comprising:

a buffer memory, receiving data from the host;

a memory controller, deploying the data in the buffer memory; and

a data cache memory, controlled by the memory controller according to a cache algorithm.

2. The data cache architecture as recited in claim 1, wherein the buffer memory is a static random access memory (SRAM).

3. The data cache architecture as recited in claim 1, wherein the memory controller comprises a micro-processor.

4. The data cache architecture as recited in claim 1, wherein the data cache memory is a synchronous dynamic random access memory (SDRAM).

5. The data cache architecture as recited in claim 1, wherein the data cache memory is partitioned into at least a plurality of large cache-size blocks and a plurality of small cache-size blocks.

6. The data cache architecture as recited in claim 1, wherein the data cache memory is partitioned into at least a plurality of large cache-size blocks, a plurality of middle cache-size blocks and a plurality of small cache-size blocks.

7. The data cache architecture as recited in claim 1, wherein the cache algorithm is achieved by a software application or a hardware implementation.

8. The data cache architecture as recited in claim 5, wherein the cache algorithm comprises steps of:

(a) determining whether the host writes data larger than or equal to a threshold number of sectors;

(b) determining whether a cache hit occurs in the large cache-size blocks;

(c) writing data to the small cache-size blocks if the host writes data smaller than the threshold number of sectors and the cache hit does not occur in the large cache-size blocks, otherwise writing data to the large cache-size blocks.

9. The data cache architecture as recited in claim 8, wherein the step (c) in the cache algorithm comprises steps of:

(c11) determining whether a cache hit occurs in the small cache-size blocks; and

(c12) writing data to the large cache-size blocks if the host writes data smaller than the threshold number of sectors and the cache hit occurs in the large cache-size blocks but does not occur in the small cache-size blocks, otherwise merging data in the small cache-size blocks to the large cache-size blocks and then writing data to the large cache-size blocks if the host writes data smaller than the threshold number of sectors and the cache hit occurs both in the large cache-size blocks and in the small cache-size blocks.

10. The data cache architecture as recited in claim 8, wherein the step (c) in the cache algorithm comprises steps of:

(c21) determining whether a cache hit occurs in the small cache-size blocks; and

(c22) writing data to the large cache-size blocks if the host writes data larger than or equal to the threshold number of sectors and the cache hit does not occur neither in the large cache-size blocks nor in the small cache-size blocks, otherwise merging data in the small cache-size blocks to the large cache-size blocks and then writing data to the large cache-size blocks if the host writes data larger than or equal to the threshold number of sectors and the cache hit occurs in the small cache-size blocks but does not occur in the large cache-size blocks.

11. The data cache architecture as recited in claim 8, wherein the step (c) in the cache algorithm comprises steps of:

(c31) determining whether a cache hit occurs in the small cache-size blocks; and

(c32) writing data to the large cache-size blocks if the host writes data larger than or equal to the threshold number of sectors and the cache hit occurs in the large cache-size blocks but does not occur in the small cache-size blocks, otherwise merging data in the small cache-size blocks to the large cache-size blocks and then writing data to the large cache-size blocks if the host writes data larger than or equal to the threshold number of sectors and the cache hit occurs both in the small cache-size blocks and in the large cache-size blocks.

12. A cache algorithm used in a data cache architecture comprising a data cache memory partitioned into at least a plurality of large cache-size blocks and a plurality of small cache-size blocks, the cache algorithm comprising steps of:

(a) determining whether a host writes data larger than or equal to a threshold number of sectors;

(b) determining whether a cache hit occurs in the large cache-size blocks;

(c) writing data to the small cache-size blocks if the host writes data smaller than the threshold number of sectors and the cache hit does not occur in the large cache-size blocks, otherwise writing data to the large cache-size blocks.

13. The cache algorithm as recited in claim 12, wherein the step (c) comprises steps of:

(c11) determining whether a cache hit occurs in the small cache-size blocks; and

(c12) writing data to the large cache-size blocks if the host writes data smaller than the threshold number of sectors and the cache hit occurs in the large cache-size blocks but does not occur in the small cache-size blocks, otherwise merging data in the small cache-size blocks to the large cache-size blocks and then writing data to the large cache-size blocks if the host writes data smaller than the threshold number of sectors and the cache hit occurs both in the large cache-size blocks and in the small cache-size blocks.

14. The cache algorithm as recited in claim 12, wherein the step (c) comprises steps of:

(c21) determining whether a cache hit occurs in the small cache-size blocks; and

(c22) writing data to the large cache-size blocks if the host writes data larger than or equal to the threshold number of sectors and the cache hit does not occur neither in the large cache-size blocks nor in the small cache-size blocks, otherwise merging data in the small cache-size blocks to the large cache-size blocks and then writing data to the large cache-size blocks if the host writes data larger than or equal to the threshold number of sectors and the cache hit occurs in the small cache-size blocks but does not occur in the large cache-size blocks.

15. The cache algorithm as recited in claim 12, wherein the step (c) comprises steps of:

(c31) determining whether a cache hit occurs in the small cache-size blocks; and

(c32) writing data to the large cache-size blocks if the host writes data larger than or equal to the threshold number of sectors and the cache hit occurs in the large cache-size blocks but does not occur in the small cache-size blocks, otherwise merging data in the small cache-size blocks to the large cache-size blocks and then writing data to the large cache-size blocks if the host writes data larger than or equal to the threshold number of sectors and the cache hit occurs both in the small cache-size blocks and in the large cache-size blocks.