Circuitry for optimization of power consumption in a system employling multiple electronic components, one of which is always powered on

• US 20090138739A1
• Filed: 11/19/2008
• Published: 05/28/2009
• Est. Priority Date: 05/27/2005
• Status: Active Grant

• Current Assignee: Medos International Sarl (Johnson & Johnson)
• Original Assignee: Codman Neuro Sciences Sarl
• Inventors: Ginggen, Alec, Crivelli, Rocco
• Granted Patent: US 9,201,484 B2
• Time in Patent Office: Days
• US Class Current: 713/324
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Circuitry for conserving power in a system employing multiple electronic components of which a first electronic component operates at a first frequency and is continuously powered on by a power source. The system further includes a second electronic component operating at a second frequency different than that of the first frequency of the first electric component, the second electronic component being maintained in a powered off state in which no energy whatsoever is consumed by the second electronic component until energized in response to a power enabling signal generated by the first electronic component based on demand of the particular function to be performed by the second electronic component. The first and second electronic components may be processors, wherein the frequency of the first processor is lower than that of the second processor.

Claims

1. Circuitry for conserving power in a system having multiple electronic components, comprising:

a power source;

a first electronic component operating at a first frequency and continuously powered on by the power source; and

a second electronic component operating at a second frequency different than that of the first frequency of the first electric component, the second electronic component being maintained in a powered off state in which no energy is consumed by the second electronic component until energized in response to a power enabling signal generated by the first electronic component based on demand of the particular function to be performed by the second electronic component.

2. The circuitry in accordance with claim 1, wherein the system further comprises a regulator for adjusting a power supply voltage to the second electronic component, the regulator and second electronic component being maintained in a powered down state until powered on in response to the power enabling signal generated by the first electronic component based on demand of the particular function to be performed by the second electronic component.

3. The circuitry in accordance with claim 2, further comprising a switch electrically coupled between the power source and the regulator, the switch being maintained in an open state until toggled to a closed state in response to the power enabling signal received from the first electronic component.

4. The circuitry in accordance with claim 1, further comprising a voltage level translator electrically coupled as an interface between the first and second electronic components operating at different voltage supply levels;

when the second electronic component is energized, the voltage level translator converting a logic data signal received as input to the first electronic component from a first power supply voltage to a second power supply voltage prior to transmission to the second electronic component; and

the voltage level translator prohibiting transmission of the data signal when the second electronic component is in a powered off state.

5. The circuitry in accordance with claim 1, wherein the system is a closed system comprising an internal device separated from an external device by a boundary, and wherein the first electronic component, second electronic component and power source are disposed within the internal device.

6. The circuitry in accordance with claim 1, wherein the first and second electronic components are first and second processors operating at different frequencies.

7. The circuitry in accordance with claim 6, wherein the first frequency of the first processor is lower than that of the second frequency of the second processor.

8. The circuitry in accordance with claim 1, wherein the first processor generates a real time clock signal to continuously count down a 24 hour time period.

9. A closed system including:

an external control device;

an internal device separated from the external device by a boundary and receiving communications from the external control device, the internal device comprising;

an internal power source;

a first processor operating at a first frequency and continuously powered by the internal power source;

a second processor operating at a second frequency higher than that of the first frequency of the first processor, the second processor being maintained in a powered off state in which no energy is consumed until powered on in response to a power enabling signal generated by the first processor based on demand to perform a particular task by the second processor;

a regulator electrically connected to adjust power supplied to the second processor;

a switch electrically connected between the internal power source and the regulator, the switch remaining in an open state until closed in response to the power enable signal generated by the first processor; and

a voltage level translator electrically coupled as an interface between the first and second processors operating at different supply voltage levels to translate a logic signal from a first power supply voltage of the first processor to a second power supply voltage of the second processor.

10. The closed system in accordance with claim 9, wherein the regulator and second processor are maintained in a powered down state until powered on in response to the power enabling signal generated by the first processor based on-demand of the particular function to be performed by the second processor.

11. The closed system in accordance with claim 9, wherein the internal device further comprises a demodulator electrically coupled to the second processor, the demodulator being maintained in a powered down state until powered on in response to the power enabling signal generated by the first processor based on demand of the particular function to be performed by the second processor.

12. The closed system in accordance with claim 9, wherein the first frequency is lower than that of the second frequency.

13. The closed system in accordance with claim 12, wherein the first processor is a real time clock for continuously counting down a 24 hour time period.

14. A method for optimizing power consumption in a system including a first electronic component operating at a first frequency and being continuously powered on by a power source, and a second electronic component electrically coupled to the first electronic component by a voltage level translator and operating at a second frequency different than that of the first frequency of the first electric component, the second electronic component being normally maintained in a powered off state in which no energy is consumed by the second electronic component, comprising the steps of:

generating a power enable signal by the first electronic component;

energizing the second electronic component in response to receiving the power enable signal generated by the first electronic component; and

when the second electronic component is in an energized state, transmitting a logic data signal converted from a first power supply voltage of the first electronic component to a second power supply voltage of the second electronic component using a voltage level translator electrically coupled as an interface between the first and second electronic components operating at different supply voltage levels;

while prohibiting transmission of the data signal to the second electronic component while in a powered off state.

15. The method in accordance with claim 14, wherein the first and second electronic components are first and second processors.

16. The method in accordance with claim 15, wherein the first frequency is lower than the second frequency.

17. The method in accordance with claim 15, wherein the first processor is a real time clock continuously counting down a 24 hour time period.

18. The method in accordance with claim 14, wherein the energizing step comprises:

closing a switch electrically coupled between the power source and a voltage regulator, the switch being normally maintained in an open state and powering on the voltage regulator and second electronic component in response to receiving the power enable signal from the first electronic component.