Data Processing Device and Method

• US 20090144522A1
• Filed: 10/24/2008
• Published: 06/04/2009
• Est. Priority Date: 03/05/2001
• Status: Active Grant

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin, Thomas, Alexander
• Granted Patent: US 8,145,881 B2
• Time in Patent Office: Days
• US Class Current: 712/15
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
• CPC Class Codes: G06F 15/17343 wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture reconfigurable processors arrays G06F15/7867
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 15/80 comprising an array of processing units with common control, e.g. single instruction multiple data processors G06F15/82 takes precedence ; for correlation function computation G06F17/15
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/803 Three-dimensional arrays or hypercubes
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path

Abstract

A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate is disclosed, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.

Claims

1. A data processing device comprising a multidimensional array of coarse grained logic elements (PAEs) processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second clock rate, wherein the first clock rate is higher than the second and wherein the coarse grained logic elements comprise storage means for storing data needed to be processed.

2. A data processing device according to claim 1 wherein the data processing of the array is controlled in a data-flow-like manner.

3. A data processing device according to claim 2, wherein the data storage means is adapted for storage of operands and/or intermediate results and wherein a valid bit is provided for each entry.

4. A data processing device according to claim 1, wherein data processing of a coarse grained logic element of the array is adapted to be effected in response to all valid bits of data and/or triggers needed being valid.

5. A processing array in particular according to claim 1, having a main data flow direction, said processing array having coarse grained logic elements and said coarse grained logic elements being adapted to effect data processing while allowing data to flow in said in one direction, in particular ALUs having an upstream input side and a data downstream output side wherein at least some of said coarse grained logic elements have data processing means such as second ALUs allowing data flow in a reverse direction.

7. A processing array according to claim 5, wherein at least one coarse grained logic element comprises an ALU in one direction and an ALU in the reverse direction.

6. A processing array according to claim 11, wherein a the instruction set for the ALUs in one direction is different from the instruction set of the ALUs in the reverse direction.

8. A processing device wherein the coarse grained element is connected to the busses and rows of coarse grained elements are provided interconnected via busses, wherein at least one input is connected to an upper row and at least one input is connected to a row below the cell and/or where this holds for an output connect.

9. A processing device according to claim 8, wherein the coarse grained element is connected to the busses and at least two input/output bus connects are provided in one row and wherein a switch in the bus structure and/or a gate or buffer or multiplexer is provided in the segment between input and/or output.

10. A method of routing a processing array adapted to automatically connect separated fragments of a configuration and/or configurations and to rip up nonconnectable traces in a stepwise manner.