READING METHOD, RESPONDER, AND INTERROGATOR

• US 20090146794A1
• Filed: 02/12/2009
• Published: 06/11/2009
• Est. Priority Date: 08/11/2003
• Status: Active Grant

• Current Assignee: Mitsuo Usami
• Original Assignee: Mitsuo Usami
• Inventors: Usami, Mitsuo
• Granted Patent: US 8,174,368 B2
• Time in Patent Office: Days
• US Class Current: 340/10.400
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: G06K 7/10039 interrogator driven, i.e. synchronous

Abstract

Transmission and reception of the identification number to/from an interrogator includes an interrogator that reads a recognition number from a responder by radio. When a clock pulse is modulated on a high-frequency carrier and transmitted to the responder from the antenna of the interrogator, there are a first case when the clock pulse interval is short and a second case when the clock pulse interval is long. By combining the clock pulse of the first case and the clock pulse of the second case so as to control the read of the recognition number from the interrogator, it is possible to realize reduction of the semiconductor chip size of the responder and suppress the cost of the semiconductor chip

Claims

1. A responder comprising:

a memory cell holds an identification number;

a first counter;

a second counter; and

an operation switching flip-flop;

wherein the second counter starts to count up second clock pulses and the memory cell reads out each bits of the identification number according to the count value of the second counter after the first counter counts up the first clock pulses from an initial value to a predetermined value.

2. The responder according to claim 1, further comprising:

a decoder;

wherein the decoder decodes count values of the second counter and outputs decoder outputs to the memory cell, and

the memory cell outputs each bits of the identification number selected by the decoder outputs.

3. The responder according to claim 1, further comprising:

a selector unit;

a first page number setting unit which holds a first page number; and

a second page number setting unit which holds a second page number;

wherein the selector unit sets either one of the first page number and the second page to the first counter as the initial number.

4. The responder according to claim 1,

wherein the interval of the first clock pulses are different from those of the second clock pulses.

5. The responder according to claim 1,

wherein the interval of the first clock pulses are longer than those of the second clock pulses.

6. The responder according to claim 1,

wherein the responder receives the first clock and the second clock pulses modulated by ASK modulation.

7. A responder comprising:

a memory cell holds an identification number;

a counter; and

an operation switching flip-flop;

wherein the first clock pulses are inputted into the counter when the operation switching flip-flop is in a set state;

second clock pulses are inputted into the counter when the operation switching flip-flop is in a reset state;

the counter counts up first clock pulses from an initial value until a count value of the first counter become zero;

after the count value of the counter become zero, the counter outputs a carry and the carry sets the operation switching flip-flop into the reset state; and

after the counter is set into the reset state, the counter starts to count up the second clock pulses and the memory cell reads out each bits of the identification number according to the count value of the second counter.

8. The responder according to claim 7,

wherein the operation switching flip-flop outputs a first signal at a first level when the operation switching flip-flop is set in a set state;

and

the operation switching flip-flop outputs a second signal at a second level when the operation switching flip-flop is in a reset state.

9. The responder according to claim 7, further comprising:

a decoder;

wherein the decoder decodes count values of the counter and outputs decoder outputs to the memory cell; and

the memory cell outputs each bits of the identification number selected by the decoder outputs.

10. The responder according to claim 7, further comprising:

a selector unit;

a first page number setting unit which holds a first page number, and

a second page number setting unit which holds a second page number,

wherein the first selector unit sets either one of the first page number and the second page to the first counter as the initial number.

11. The responder according to claim 7,

wherein the interval of the first clock pulses are different from those of the second clock pulses.

12. The responder according to claim 7,

wherein the interval of the first clock pulses are longer than those of the second clock pulses.

13. The responder according to claim 7,

wherein the responder receives the first clock pulses and the second clock pulses modulated by ASK modulation.