THIN-FILM TRANSISTOR, SUBSTRATE AND DISPLAY DEVICE EACH HAVING THE THIN-FILM TRANSISTOR, AND METHOD OF MANUFACTURING THE THIN-FILM TRANSISTOR

• US 20090152553A1
• Filed: 08/08/2008
• Published: 06/18/2009
• Est. Priority Date: 12/18/2007
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Choi, Yong-Mo, Choi, Jae-Ho, Oh, Hwa-Yeul, Yang, Sung-Hoon, YOON, Kap-Soo, Kim, Sung-Ryul
• Granted Patent: US 8,189,131 B2
• Time in Patent Office: Days
• US Class Current: 257/59
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/78687 with a multilayer structure or superlattice structure
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin-film transistor (TFT) includes a gate electrode, a semiconductor pattern, a source electrode, and a drain electrode. The semiconductor pattern includes an active layer being overlapped with the gate electrode and a low band gap portion having a lower energy band gap than the active layer. The source and drain electrodes are spaced apart from each other to be overlapped with the semiconductor pattern. Therefore, the semiconductor pattern includes a low band gap portion having a lower energy band gap than the active layer, so that electron mobility may be increased in a channel formed along the low band gap portion so that electric characteristics of the TFT may be enhanced.

Claims

1. A thin-film transistor (TFT) comprising:

a gate electrode;

a semiconductor pattern comprising an active layer being overlapped with the gate electrode and a low band gap portion having a lower energy band gap than the active layer; and

a source electrode and a drain electrode being spaced apart from each other to be overlapped with the semiconductor pattern.

2. The TFT of claim 1, further comprising a gate insulation layer formed between the gate electrode and the low band gap portion.

3. The TFT of claim 2, wherein the active layer comprises amorphous silicon or microcrystalline silicon.

4. The TFT of claim 3, wherein the low band gap portion comprises a plurality of nanocrystals that are spaced apart from each other between the gate insulation layer and the active layer.

5. The TFT of claim 4, wherein the nanocrystals comprises silicon or a silicon germanium (Si_xGe_1-x, wherein 0<

x<

1).

6. The TFT of claim 4, wherein the nanocrystals are spaced apart from each other in a plane direction that is parallel with a surface of the gate insulation layer to have a shape of two-dimensional electron gas.

7. The TFT of claim 4, wherein an energy band gap of the low band gap portion is about 0.9 eV to about 1.8 eV.

8. The TFT of claim 3, wherein the low band gap portion comprises a low band gap layer formed between the gate insulation layer and the active layer in a thin-film shape.

9. The TFT of claim 8, wherein the low band gap layer comprises a silicon germanium (Si_xGe_1-x, wherein 0<

x<

1).

10. The TFT of claim 8, wherein an energy band gap of the low band gap layer is about 0.9 eV to about 1.8 eV.

11. The TFT of claim 3, wherein the semiconductor pattern further comprises a buffer layer between the gate insulation layer and the low band gap portion, wherein the buffer layer and the active layer are formed from a same material.

12. The TFT of claim 3, wherein the semiconductor pattern further comprises an ohmic contact layer formed between the source electrode and the active layer, and between the drain electrode and the active layer.

13. A method of manufacturing a thin-film transistor (TFT), the method comprising:

forming a gate electrode;

forming a semiconductor pattern comprising an active layer being overlapped with the gate electrode and a low band gap portion having a lower energy band gap than the active layer; and

forming a source electrode and a drain electrode that are spaced apart from each other to be overlapped with the semiconductor pattern.

14. The method of claim 13, further comprising forming a gate insulation layer between the gate electrode and the low band gap portion.

15. The method of claim 14, further comprising forming a buffer layer between the gate insulation layer and the low band gap portion, wherein the buffer layer and the active layer are formed from a same material.

16. The method of claim 14, wherein forming the semiconductor pattern comprises:

forming the low band gap portion on the gate insulation layer; and

forming the active layer on the low band gap portion.

17. The method of claim 16, wherein forming the low band gap portion comprises depositing silicon or germanium on the gate insulation layer to form a plurality of nanocrystals that are spaced apart from each other.

18. The method of claim 16, wherein forming the low band gap portion comprises depositing silicon or germanium on the gate insulation layer to form a low band gap layer of a thin-film shape.

19. A thin-film transistor (TFT) substrate comprising:

a base substrate;

a plurality of TFTs comprising;

a gate electrode;

a semiconductor pattern comprising an active layer being overlapped with the gate electrode and a low band gap portion having a low energy band gap than the active layer; and

a source electrode and a drain electrode that are spaced apart from each other to be overlapped with the semiconductor pattern;

a passivation layer covering the TFT to protect the TFT; and

a plurality of pixel electrodes formed on the passivation layer to be electrically connected to the TFT through a plurality of contact holes of the passivation layer.

20. The TFT substrate of claim 19, wherein a portion of the TFTs is formed in a display area of the base substrate to be electrically connected to the pixel electrodes, respectively, and

another portion of the TFT is formed in a peripheral area of the base substrate to control the TFT formed in the display area.

21. A display device comprising:

a thin-film transistor (TFT) substrate;

an opposite substrate opposite to the TFT substrate; and

a liquid crystal layer disposed between the TFT substrate and the opposite substrate, wherein the TFT substrate comprises;

a base substrate;

a plurality of TFTs comprising a gate electrode, a semiconductor pattern comprising an active layer being overlapped with the gate electrode and a low band gap portion having a low energy band gap than the active layer, and a source electrode and a drain electrode that are spaced apart from each other to be overlapped with the semiconductor pattern;

a passivation layer covering the TFT to protect the TFT; and

a plurality of pixel electrodes formed on the passivation layer to be electrically connected to the TFT through a plurality of contact holes of the passivation layer.