METHOD AND APPARATUS FOR MODELING SOURCE-DRAIN CURRENT OF THIN FILM TRANSISTOR

• US 20090157372A1
• Filed: 08/29/2008
• Published: 06/18/2009
• Est. Priority Date: 12/17/2007
• Status: Active Grant

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: SHIN, Jae Heon, Chu, Hye Yong, Hwang, Chi Sun, Ryu, Min Ki, Cheong, Woo Seok
• Granted Patent: US 8,095,343 B2
• Time in Patent Office: Days
• US Class Current: 703/13
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

Provided are a method and apparatus for modeling source-drain current of a TFT. The method includes receiving sample data, the sample data including a sample input value and a sample output value; adjusting modeling variables according to the sample data; calculating a current model value according to the adjusted modeling variables; when a difference between the calculated current model value and the sample output value is smaller than a predetermined threshold value, fitting a current model by applying the adjusted modeling variables to the current model; applying actual input data to the fitted current model; and outputting a result value corresponding to the actual input data, wherein the current model is a model for predicting the source-drain current of the TFT.

Claims

1. A method for modeling source-drain current of a thin film transistor (TFT), comprising:

receiving sample data, the sample data including a sample input value and a sample output value;

adjusting modeling variables according to the sample data;

calculating a current model value according to the adjusted modeling variables;

when a difference between the calculated current model value and the sample output value is smaller than a predetermined threshold value, fitting a current model by applying the adjusted modeling variables to the current model;

applying actual input data to the fitted current model; and

outputting a result value corresponding to the actual input data, wherein the current model is a model for predicting the source-drain current of the TFT.

2. The method of claim 1, wherein the current model is determined by the following equation:

I_DS=I_leak+(1/I_b+1/I_a)<sup>−

1</sup>, where I_DS denotes drain-source current, I_leak denotes leakage current of a TFT, I_b denotes a first current value that is a source-drain current value calculated in a regime below a threshold voltage, and Ia denotes a second current value that is a source-drain current value calculated in a regime above a threshold voltage.

3. The method of claim 1, wherein the TFT is one of an organic TFT, an oxide TFT and an amorphous silicon TFT.

4. The method of claim 1, wherein the sample input value comprises a drain voltage value and a gate voltage value, and the sample output value is a source-drain current value measured according to the sample input value.

5. The method of claim 2, wherein the first current value is determined by equations:

I_b=(WC/L) (K_b/(b+2)) (V_GF^b+2−

(V_GF−

V_D)^b+2) when V_GF>

0, and

I_b=0 when V_GF≦

0

where V_GF denotes a difference between a gate voltage and a flat band voltage, W denotes a channel width, C denotes gate insulating capacitance, L denotes a channel length, V_D denotes a drain voltage, and K_b and b denote modeling variable values.

6. The method of claim 2, wherein the second current value is determined by the following equation:

I_a=(WC/L) (K_a/(a+2)) (V_GTe^a+2−

(V_GTe−

V_D)^a+2),

where V_GTe=(V_min/2) (1+(V_GT/V_min)+(Δ

²+(V_GT/V_min−

1)²)^0.5), V_GT denotes a difference between a gate voltage and a threshold voltage, W denotes a channel width, C denotes gate insulating capacitance, L denotes a channel length, V_D denotes a drain voltage, V_min denotes a minimum voltage, Ka and a denote modeling variable values, and Δ

denotes a variable indicating convergence strength.

7. An apparatus for modeling source-drain current of a TFT, comprising:

a sample-data input unit for receiving sample data, the sample data including a sample input value and a sample output value;

a variable adjusting unit for adjusting modeling variables according to the sample data;

a model calculating unit for calculating a current model value according to the adjusted modeling variables;

an error calculating unit for calculating a difference between the calculated current model value and the sample output value;

an error determining unit for determining whether the difference is smaller than a predetermined threshold value, and establishing the adjusted modeling variables when the difference is smaller than the predetermined threshold value;

a model applying unit for applying the modeling variables established by the error determining unit to the current model; and

a result-value output unit for applying actual input data to the current model and outputting a result value corresponding to the actual input data,

wherein the current model is a model for predicting the source-drain current of the TFT.

8. The apparatus of claim 7, wherein the current model is determined by the following equation:

I_DS=I_leak+(1/I_b+1/I_a)<sup>−

1</sup>, where I_DS denotes drain-source current, I_leak denotes leakage current of a TFT, I_b denotes a first current value that is a source-drain current value calculated in a regime below a threshold voltage, and I_a denotes a second current value that is a source-drain current value calculated in a regime above a threshold voltage.

9. The apparatus of claim 8, wherein the first current value and the second current value are applied based on the threshold voltage.

10. The apparatus of claim 7, wherein the TFT is one of an organic TFT, an oxide TFT and an amorphous silicon TFT.

11. The apparatus of claim 7, wherein the sample input value comprises a drain voltage value and a gate voltage value, and the sample output value is a source-drain current value measured according to the sample input value.

12. The apparatus of claim 8, wherein the first current value is determined by the following equation:

I_b=(WC/L) (K_b/(b+2)) (V_GF^b+2−

(V_GF−

V_D)^b+2) when V_GF>

0, and

I_b=0 when V_GF≦

0

where V_GF denotes a difference between a gate voltage and a flat band voltage, W denotes a channel width, C denotes gate insulating capacitance, L denotes a channel length, V_D denotes a drain voltage, and K_b and b denote modeling variable values.

13. The apparatus of claim 8, wherein the second current value is determined by the following equation:

I_a=(WC/L) (K_a/(a+2)) (V_GTe^a+2−

(V_GTe−

V_D)^a+2),

where V_GTe=(V_min/2) (1+(V_GT/V_min)+(Δ

²+(V_GT/V_min−

1)²)^0.5), V_GT denotes a difference between a gate voltage and a threshold voltage, W denotes a channel width, C denotes gate insulating capacitance, L denotes a channel length, V_D denotes a drain voltage, V_min denotes a minimum voltage, K_a and a denote modeling variable values, and Δ

denotes a variable indicating convergence strength.