Memory Apparatus and Method of Evenly Using the Blocks of a Flash Memory

• US 20090157947A1
• Filed: 12/14/2007
• Published: 06/18/2009
• Est. Priority Date: 12/14/2007
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Inventors: Lin, Chien-Cheng, Chang, Wen-Chung
• Granted Patent: US 8,122,179 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A memory apparatus and a method of evenly using the blocks of a flash memory are provided. The memory apparatus comprises a flash memory and a controller. The flash memory comprises a data region with a plurality of data blocks and a spare region with a plurality of spare blocks. The controller is configured to receive data corresponding to the first data block, select a spare block, program data into the spare block when the erase count corresponding to the spare block is less than the predetermined value or to select a second data block and program data stored in the second data block into the spare block when the erased count corresponding to the spare block reaches the predetermined value. As a result, the blocks of the flash memory are used evenly.

Claims

1. A method for accessing a flash memory, the flash memory is divided into a data region and a spare region, the data region includes a plurality of data blocks and the spare region includes a plurality of spare blocks, the method comprising the steps of:

receiving data corresponding to a first logical address;

selecting a spare block in the spare region;

programming data into the spare block; and

linking a physical address of the spare block to the first logical address.

2. The method as claimed in claim 1, wherein the spare block is at a head sequence in the spare region.

3. The method as claimed in claim 1, wherein the spare block is selected when an erased count corresponding to the spare block is less than a predetermined value.

4. The method as claimed in claim 3, wherein the predetermined value is a fixed value or a ranged value, which is preset in a firmware stored in the flash memory or in a controller.

5. The method as claimed in claim 1, further comprising the steps of:

erasing the first data block; and

recycling the first data block at a tail sequence in the spare region.

6. A method of averagely using blocks of a flash memory, the flash memory includes a data region and a spare region, the data region having a plurality of data blocks, the spare region having a plurality of spare blocks, the method comprising the steps of:

receiving data corresponding to a first data block;

selecting a spare block which is at a head sequence in the spare region;

selecting a second data block when an erased count corresponding to the spare block reaches a predetermined value;

programming data stored in the second data block into the spare block; and

remapping the second data block and the spare block.

7. The method as claimed in claim 6, wherein erased count corresponding to the second data block equals to zero.

8. The method as claimed in claim 6, wherein step of selecting the second data block further comprises the step of:

searching for a zero erased count among a plurality of erased counts corresponding to each one of the data blocks.

9. The method as claimed in claim 8, further comprising the step of:

subtracting one from each of the erased counts corresponding to all of blocks if there is no data block having the zero erased count.

10. The method as claimed in claim 6, wherein the second data block is selected by searching for a least erased count among a plurality of erased counts corresponding to each one of the data blocks.

11. The method as claimed in claim 6, further comprising the steps of:

erasing the second data block; and

recycling the second data block at a tail sequence in the spare region.

12. The method as claimed in claim 6, wherein the remapping step further comprises the step of:

linking a physical address of the spare block to a logical address of the second data block.

13. The method as claimed in claim 6, wherein the predetermined value is a fixed value or a ranged value, which is preset in a firmware stored in the flash memory or in a controller.

14. A memory apparatus, comprising:

a flash memory including a data region having a plurality of data blocks and a spare region having a plurality of spare blocks; and

a controller being configured to receive data corresponding to a first data block, to select a spare block, to program data into the spare block when an erased count corresponding to the spare block is less than a predetermined value or to select a second data block and program data stored in the second data block into the spare block when the erased count corresponding to the spare block reaches the predetermined value, whereby averagely using blocks of the flash memory.

15. The memory apparatus as claimed in claim 14, the controller further comprising a buffer memory for temporarily storing linking information about logical address and physical address of the blocks of the flash memory.

16. The memory apparatus as claimed in claim 15, wherein the linking information includes a plurality of erased counts corresponds to physical addresses of each of blocks and the linking information with erased counts being stored into one of block of flash memory after an operation of access.

17. The memory apparatus as claimed in claim 16, wherein the erased counts are relative value, not absolute value.

18. The memory apparatus as claimed in claim 14, wherein the second data block is selected by searching for a zero erased count among a plurality of erased counts corresponding to each one of the data blocks.

19. The memory apparatus as claimed in claim 18, wherein the controller is configured to subtract one from each of the erased counts corresponding to all of blocks if there is no data block having the zero erased count.

20. The memory apparatus as claimed in claim 14, wherein the predetermined value is a fixed value or a ranged value, which is preset in a firmware stored in the flash memory or in the controller.