High electron mobility transistor having self-aligned miniature field mitigating plate and protective dielectric layer and fabrication method thereof

• US 20090159930A1
• Filed: 12/20/2007
• Published: 06/25/2009
• Est. Priority Date: 12/20/2007
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Space & Mission Systems Corporation (Northrop Grumman Corporation)
• Inventors: Smorchkova, loulia, Heying, Ben, Liu, Po-Hsin, Hikin, Boris, Namba, Carol, Coffie, Robert
• Granted Patent: US 7,750,370 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A semiconductor device is fabricated to include source and drain contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer; a protective dielectric layer disposed between the source and drain contacts on the barrier layer; a metallization layer disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.

Claims

1. A method of forming a semiconductor device on a semiconductor substrate including a protective dielectric layer disposed on the semiconductor substrate, the method comprising:

forming drain and source ohmic vias in the protective dielectric layer;

depositing ohmic metal into the drain and source ohmic vias to form drain and source contacts;

forming a resist layer on the protective dielectric layer and the drain and source contacts;

forming a resist opening in the resist layer;

etching a predetermined portion of the protective dielectric layer via the resist opening to form a window in the protective dielectric layer;

widening the resist opening so that a width of a lower portion of the resist opening is greater than a width of the window in the protective dielectric layer;

depositing a metal film in the window and the resist opening; and

lifting off the resist layer to form a T-gate and a field mitigating plate disposed at a side portion of the T-gate on the semiconductor substrate.

2. The method of claim 1, wherein the depositing of the ohmic metal into the drain and source ohmic vias further includes depositing the ohmic metal into predetermined portions of the drain and source ohmic vias so that ohmic vias gaps remain in the drain and source ohmic vias between the deposited ohmic metal and the protective dielectric layer.

3. The method of claim 2, further comprising:

annealing the deposited ohmic metal at a predetermined temperature; and

subsequently depositing metallizations in the ohmic vias gaps.

4. The method of claim 1, wherein the etching of the predetermined portion of the protective dielectric layer via the resist opening to form the window in the protective layer further includes performing the etching by applying an anisotropic dry etch to the predetermined portion of the protective dielectric layer.

5. The method of claim 1, wherein the widening of the resist opening further includes performing a post-etch oxygen descum on the resist opening so that the resist opening is widened while a width of the window in the protective dielectric layer is not substantially effected.

6. The method of claim 1, wherein the protective dielectric layer comprises one of silicon nitride (SiN) and aluminum nitride.

7. The method of claim 1, wherein the protective dielectric layer includes a combination of silicon nitride and aluminum nitride.

8. The method of claim 1, wherein the protective dielectric layer is deposited using molecular beam epitaxy growth (MBE) on a surface of the semiconductor substrate.

9. The method of claim 1, wherein a length of the metal T-gate is less than 0.25 micrometers, and a length of the field mitigating plate is less than 50 nanometers.

10. The method of claim 1, wherein the protective dielectric layer is formed by:

forming a first dielectric layer on the semiconductor substrate;

forming an etch-stop layer on the first dielectric layer; and

forming a second dielectric protective layer on the etch-stop layer,

wherein the etching of the predetermined portion of the protective dielectric layer to form the window further includes etching a predetermined portion of the second dielectric layer and the etch-stop layer via the resist opening to form the window in the second dielectric layer and the etch-stop layer.

11. A high electron mobility transistor (HEMT), comprising:

a semi-insulating substrate;

a channel layer disposed on the substrate;

an barrier layer disposed over the channel layer;

drain and source contacts including an ohmic metal sunken into the barrier layer and a portion of the channel layer;

a protective dielectric layer disposed between the drain and source contacts on the barrier layer;

metallizations disposed in drain and source ohmic vias between the source contact and the protective dielectric layer and between the protective dielectric layer and the drain contact; and

a metal T-gate disposed above the barrier layer including a field mitigating plate disposed on a side portion of a stem of the metal T-gate.

12. The HEMT of claim 11, wherein the channel layer comprises gallium nitride (GaN) and the barrier layer comprises aluminum gallium nitride (AlGaN).

13. The HEMT of claim 11, wherein a length of the metal T-gate is less than 0.25 micrometers.

14. The HEMT of claim 11, wherein a length of the field mitigating plate is less than 50 nanometers.

15. The HEMT of claim 11, wherein the metal T-gate is further disposed in a predetermined portion of the protective dielectric layer, and the field mitigating plate is disposed on another predetermined portion of the protective dielectric layer.

16. The HEMT of claim 11, wherein the protective dielectric layer further includes:

a first dielectric layer disposed on the barrier layer;

an etch-stop layer disposed on the first dielectric layer; and

a second dielectric layer disposed on the etch-stop layer;

wherein the metal T-gate is further disposed in a predetermined portion of the second protective dielectric layer, and the field mitigating plate is disposed on the second protective dielectric layer.

17. A method of forming a high electron mobility transistor (HEMT) device including:

a semi-insulating substrate;

a channel layer disposed above the semi-insulating substrate;

a barrier layer disposed over the channel layer, the barrier layer inducing a 2-DEG layer at an interface between the barrier layer and the channel layer, the method comprising;

coating the barrier layer with a dielectric material to form a protective dielectric layer;

forming drain and source ohmic vias in the protective dielectric layer;

depositing ohmic metal into the drain and source ohmic vias to form drain and source contacts;

forming a resist layer on the protective dielectric layer and the drain and source contacts;

forming a resist opening in the resist layer;

etching a predetermined portion of the protective dielectric layer via the resist opening to form a window in the protective dielectric layer;

widening the resist opening so that a width of a lower portion of the resist opening is greater than a width of the window in the protective dielectric layer;

depositing a metal film in the window and the resist opening; and

lifting off the resist layer to form a T-gate and a field mitigating plate disposed at a side portion of the T-gate.

18. The method of claim 17, wherein the depositing of the ohmic metal into the drain and source ohmic vias to form drain and source contacts further includes:

depositing the ohmic metal into predetermined portions of the drain and source ohmic vias to form ohmic via gaps between the ohmic metal and the protective dielectric layer;

annealing the ohmic metal at a predetermined high temperature so that the ohmic metal sinks into the barrier layer; and

depositing metallizations in the ohmic via gaps.

19. The method of claim 17, wherein the coating of the barrier layer with the dielectric material further included forming silicon nitride on the barrier layer by molecular beam epitaxy (MBE).

20. The method of claim 17, wherein the coating the barrier layer with the dielectric material to form the protective dielectric layer further comprises:

coating the barrier layer with the dielectric material to form a first dielectric layer;

coating the first dielectric layer with an etch-stop material to form an etch-stop layer on the first dielectric layer; and

coating the etch-stop layer with the dielectric material to form a second dielectric layer on the etch-stop layer.