Flash memory controller and system including data pipelines incorporating multiple buffers

• US 20090172260A1
• Filed: 04/08/2008
• Published: 07/02/2009
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Pliant Technology, Inc. (Western Digital Corporation)
• Inventors: Prins, Douglas A, Olbrich, Aaron K.
• Granted Patent: US 8,738,841 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is moved between the storage module and one or more hosts.

Claims

1. A system including a flash memory controller and flash memory devices, the system comprising:

a first set of buffers, at least one of which stores a page of data read from a flash memory device;

a second set of buffers, a first of which stores data read from a plurality of buffers from the first set of buffers, the data relating to a first host command, the second set of buffers being operably connected to the first set of buffers by a first direct or indirect transmission path;

a third buffer or set of buffers, holding data read from a plurality of buffers from the second set, the data relating to a plurality of host commands;

the third buffer or set being operably connected to the second set of buffers by a second direct or indirect transmission path; and

a fourth buffer or set of buffers holding data read from the third buffer, the data relating to a second host command;

the fourth buffer or set being operably connected to the third buffer or set by a third direct or indirect transmission path and to a host port.

2. The system as in claim 1, in which:

the first transmission path transmits data at a first rate, and the second transmission path transmits data at a second, higher rate.

3. The system as in claim 2, in which:

the first transmission path includes parallel paths between a first group of buffers from the first set and the first buffer from the second set, the parallel paths simultaneously transmitting data in each direction between the first group of buffers from the first set and the first buffer from the second set.

4. The system as in claim 3, in which:

the first transmission path further includes parallel paths between a second group of buffers from the first set and a second buffer from the second set, the parallel paths simultaneously transmitting data in each direction between the second group of buffers from the first set and the second buffer from the second set, and

the first transmission path lacks any connection between the first group of buffers from the first set and the second buffer from the second set, or between the second group of buffers from the first set and the first buffer from the second set.

5. The system as in claim 4, in which:

the second buffer from the second set stores data read from the second group of buffers from the first set, the data relating to a third host command.

6. A system including a flash storage controller and a plurality of flash memory devices divided into groups, the system comprising:

a first set of buffers, each buffer communicating over a first direct or indirect signal path with a set of flash memory devices and over a second direct or indirect signal path with a first buffer not part of the first set, the first path transmitting data at a first rate and the second path transmitting data at a second, higher rate;

the first set of buffers including a second buffer and a third buffer, the second buffer holding data relating to a first host command, the data having been received from a first group of flash memory devices, the third buffer holding data relating to the first host command, the data having been received from a second group of flash memory devices,

the first set of buffers further including a fourth buffer, the fourth buffer holding data received from a third group of flash memory devices, the data relating to a second host command.

7. The system as in claim 6, in which:

the first set of buffers includes a fifth buffer, the fifth buffer holding data received from the first buffer for transmission to a fourth group of flash memory devices.

8. The system as in claim 7, in which:

the data stored in the fifth buffer relates to a third host command.

9. The system as in claim 8, further including:

a sixth buffer, communicating over a third direct or indirect signal path with a host port and over a fourth direct or indirect signal path with the first buffer, the sixth buffer containing data received from the first buffer, the data relating to a fourth host command.

10. The system as in claim 9, further including:

a seventh buffer, communicating over a fifth direct or indirect signal path with a host port and over a sixth direct or indirect signal path with the first buffer, the sixth buffer containing data received from the host port, the data relating to a fifth host command.

11. A method of operating a storage system including a controller and a plurality of flash memory devices, comprising the following steps:

(a) transferring first data related to a first host command from a first flash memory device to a first buffer associated with the first flash memory device and transferring second data related to the first host command from a second flash memory device to a second buffer associated with the second flash memory device, the transfers occurring substantially simultaneously;

(b) transferring the first data and the second data to a third buffer, the transfers occurring substantially simultaneously,

(c) transferring the first data and the second data to a fourth buffer;

(d) at the fourth buffer, aggregating the first data and the second data with third data, the third data also relating to the first host command;

(e) transferring the aggregated first, second and third data to a fifth buffer;

(f) transferring the aggregated first, second and third data from the fifth buffer to a host through a host port.

12. The method as in claim 11, further including:

(g) transferring fourth data related to a second host command from a third flash memory device to a sixth buffer associated with the third flash memory device and transferring fifth data related to the second host command from a fourth flash memory device to a seventh buffer associated with the fourth flash memory device, the transfers occurring substantially simultaneously;

(h) transferring the fourth data and the fifth data to an eighth buffer, the transfers occurring substantially simultaneously,

(i) transferring the fourth data and the fifth data to the fourth buffer;

(j) at the fourth buffer, aggregating the fourth data and the fifth data with sixth data, the sixth data also relating to the second host command;

whereby, the fourth buffer simultaneously holds data relating to the first host command and the second host command.

13. The method as in claim 12, further including:

(k) in a ninth buffer, receiving seventh data related to a third host command, the data being received through the host port;

(l) transferring the seventh data from the ninth buffer to the fourth buffer;

whereby, the fourth buffer simultaneously holds data relating to the first host command, the second host command and the third host command.

14. The method as in claim 13, further including:

(m) transferring the seventh data from the fourth buffer to a tenth buffer;

(n) transferring a first portion of the seventh data from the tenth buffer to an eleventh buffer, the eleventh buffer associated with a fifth flash memory device, and transferring a second portion of the seventh data from the tenth buffer to a twelfth buffer, the twelfth buffer associated with a seventh flash memory device, the transfers occurring substantially simultaneously;

(o) writing the first portion of the seventh data from the eleventh buffer into the cells of the fifth flash memory device and writing the second portion of the seventh data from the twelfth buffer into the cells of the sixth flash memory device, the writing operations occurring substantially simultaneously.

15. The method as in claim 11, in which

the step (b) transfer occurs at a first data rate;

and

the step (c) transfer occurs at a second, higher data rate.

16. A flash memory controller comprising:

a first group of buffers including a first buffer, a second buffer and a third buffer, each buffer from the first group communicating with one or more flash memory devices, the first buffer holding first data transferred from a first flash memory device and the second buffer holding second data transferred from a second flash memory device, the first data relating to a first host command and the second data related to a second host command;

a first set of transmission paths between each buffer from the first group and one or more flash memory devices, the first set of transmission paths communicating data at a first rate;

a fourth buffer communicating with each buffer in the first buffer group, the fourth buffer holding data relating to two separate host commands, and

a second set of transmission paths between the fourth buffer and the first buffer group, the second set of transmission paths communicating data at a second rate, the second rate being higher than the first rate.

17. The flash memory controller as in claim 16, in which:

the fourth buffer stores third data received from the first buffer and fourth data received from the second buffer, the third data relating to the first host command and the fourth data relating to the second host command.

18. The flash memory controller as in claim 17, in which:

the third data is held in a first memory structure and the fourth data is held in a second memory structure, and

the first memory structure includes a first gap that does not contain data, and the first data is associated with information that identifies the first gap; and

the second memory structure includes a second gap that does not contain data, and the second data is associated with information that identifies the second gap.

19. The flash memory controller as in claim 18, in which:

the fourth buffer holds fifth data received from a first host, the fifth data associated with a third host command.

20. The flash memory controller as in claim 19, in which:

the fourth buffer holds sixth data received from a second host, the sixth data associated with a fourth host command.

21. The flash memory controller as in claim 20, in which:

the first, second and third buffers are located on a single integrated circuit device.

22. The flash memory controller as in claim 20, in which

the first set of transmission paths connects the first buffer from the first group with the first flash memory device, but not the second flash memory device and connects the second buffer from the first group with the second flash memory device but not the first flash memory device.

23. A flash memory controller comprising:

a first group of buffers including a first buffer, a second buffer and a third buffer, each buffer from the first group communicating with one or more flash memory devices, the first buffer holding first data transferred from a first flash memory device and the second buffer holding second data transferred from a second flash memory device;

a fourth buffer storing third data received from the first buffer and fourth data received from the second buffer.

the third data being held in a first memory structure and the fourth data being held in the second memory structure;

the first memory structure including a first gap that does not contain data, and the first data is associated with information that identifies the first gap; and

the second memory structure includes a second gap that does not contain data, and the second data is associated with information that identifies the second gap.

24. The flash memory controller as in claim 23 in which:

the first data relates to a first host command, the second data relates to a second host command and the third data relates to a third host command; and

the fourth buffer holds fifth data, the fifth data associated with a fourth host command.

25. The flash memory controller as in claim 24, in which:

the first, second and third buffers are located on a single integrated circuit device.