Patrol function used in flash storage controller to detect data errors

• US 20090172499A1
• Filed: 04/08/2008
• Published: 07/02/2009
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Pliant Technology, Inc. (Western Digital Corporation)
• Inventors: Prins, Douglas A., Olbrich, Aaron K.
• Granted Patent: US 8,245,101 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A patrol function performed in a storage controller connected to a flash memory storage module. The function causes selected areas of the flash storage to be read for purposes of detecting and correcting errors.

Claims

1. In a storage controller attached to a host and to a flash memory module made up of a plurality of flash memory devices, the flash memory devices being organized in groups, each group including a plurality of areas, a method comprising the following steps:

(a) performing a first read of first data and first ECC information from a first area of a first group;

(b) generating second ECC information relating to the first data;

(c) comparing the first and second ECC information;

(d) if the first and second ECC information do not match, performing an ECC correction operation on the first data, the ECC correction operation if successful resulting in corrected first data and a value specifying the number of corrected errors; and

performing steps (e) and (f) if the ECC correction operation was successful;

(e) if the number of corrected errors exceeds a threshold, writing the corrected first data to an area of the first group other than the first area of the first group and setting an indicator indicating that the data contained in the first area of the first group is invalid;

(f) if the number of corrected errors does not exceed the threshold, discarding the corrected first data without writing the corrected first data to the flash memory module, the discarding occurring in connection with a subsequent ECC correction operation.

2. The method as in claim 1, further including:

performing steps (a) through (f) for a first area of a second group, the performance of at least one step for the first area of the first group overlapping in time the performance of the same step for the first area of the second group.

3. The method as in claim 1, in which:

steps (a)-(f) are repeated for substantially all areas of the first group that contain valid data.

4. The method as in claim 1, in which:

step (a) is preceded by a step of determining whether a storage controller worklist contains one or more tasks, with step (a) being deferred until after any such tasks have been handled.

5. The method as in claim 1, in which step (d) further includes:

if the ECC correction operation fails because the number of errors exceeds the number of errors that can be corrected in a single pass, repeating the ECC correction operation, and, if the repeated ECC correction operation is successful, performing steps (e) and (f).

6. The method as in claim 5, in which step (d) further includes:

following failure of an ECC correction operation because the number of errors exceeds the number of errors that can be corrected in a single pass, reading the first data a second time and performing a first OR'"'"'ing operation that Ors together the results of the first read of the first data and the second read of the first data.

7. The method as in claim 6, in which step (d) further includes:

following the first OR'"'"'ing operation, using the first ECC information to perform an ECC correction operation on the results of the first OR'"'"'ing operation, and, if the ECC correction operation on the results of the first OR'"'"'ing operation is successful, performing steps (e) and (f).

8. The method as in claim 7, in which step (d) further includes:

if an ECC correction operation on the results of the first OR'"'"'ing operation fails because the number of errors exceeds the number of errors that can be corrected in one pass, performing a second OR'"'"'ing operation, using a third read of the first data and the results of the first OR'"'"'ing operation as inputs to the second OR'"'"'ing operation, and repeating the ECC correction operation using the results of the second OR'"'"'ing operation and the first ECC information.

9. In a system including a storage controller and a flash memory module made up of at least three flash memory groups, performing the following steps for each of the groups:

(a) checking to determine if a worklist associated with the group contains any tasks and performing the following steps if no tasks are found;

(b) performing a flash memory read relating to an area of the group;

(c) performing an ECC check related to data read from the area;

(d) performing an action if the ECC check reveals errors;

(e) repeating steps (a) through (d) for substantially all areas of the flash group that contain currently valid data received as a result of a host-initiated write;

whereby, at least steps (a)-(c) are performed independently for each flash memory group.

10. The method as in claim 9, in which:

the step (d) action includes using ECC information to attempt to correct errors in the data read in step (b).

11. The method as in claim 10, in which:

if the step (d) attempt is successful, the step (d) action further includes writing the corrected data to the flash memory module, the corrected data being written to the same flash memory group from which the uncorrected data was originally read, but to a different area from that group than the area from which the uncorrected data was originally read, the writing only occurring if the number of corrected errors exceeds a first threshold.

12. The method as in claim 11, in which:

the first threshold is less than the number of errors that can be corrected in a single ECC correction operation.

13. The method as in claim 12, in which:

if the step (d) attempt is unsuccessful, performing a second error correction operation using the ECC information, and, if the second error correction operation is successful, writing the corrected data to the flash memory module, the corrected data being written to the same flash memory group from which the uncorrected data was originally read, but to a different area from that group than the area from which the uncorrected data was originally read, the writing only occurring if the number of corrected errors exceeds the first threshold.

14. The method as in claim 13, in which:

if the second error correction operation is unsuccessful, OR'"'"'ing together the results of two or more flash memory reads and performing a third error correction operation using the ECC information and the results of the OR'"'"'ing operation, and, if the third error correction operation is successful, writing the corrected data to the flash memory module, the corrected data being written to the same flash memory group from which the uncorrected data was originally read, but to a different area from that group than the area from which the uncorrected data was originally read, the writing only occurring if the number of corrected errors exceeds the first threshold.

15. The method as in claim 13, further including:

(f) following completion of step (e), waiting until a specified event and repeating steps (a) through (e).

16. The method as in claim 15, in which:

the specified event is selected based at least in part on a value entered by a user of the system.

17. In a system including a storage controller and a flash memory module, a method comprising the following steps:

(a) identifying an entry in a metadata table, the identification based on information in the entry, the information designating a first portion of the flash memory module;

(b) reading first data and first ECC information associated with the entry;

(c) generating second ECC information based on the first data;

(d) comparing the first and second ECC information;

(e) if the first and second ECC information differ, performing a first ECC correction operation based on the first ECC information;

(f) if the first ECC correction operation is successful and if the number of errors corrected exceeds a threshold, writing the corrected data to the flash memory module and invalidating the entry;

whereas, if the number of errors corrected does not exceed the threshold, the corrected data is not written to the flash memory.

18. The method as in claim 17, further including:

(g) if the first ECC correction operation is not successful, reading the first data a second time and performing a second ECC correction operation, and, if the second ECC correction operation is successful and if the number of errors corrected exceeds a threshold, writing the corrected data to the flash memory module and invalidating the entry.

19. The method as in claim 18, in which step (g) further includes:

a first operation of OR'"'"'ing together the results of the first read of the first data and the second read of the first data and using the results of the first OR'"'"'ing operation and the first ECC information as inputs to the second ECC correction operation.

20. The method as in claim 19, further including:

(h) if the second ECC correction operation is not successful, reading the first data a third time and using the results of the first OR'"'"'ing operation and the third read of the first data as inputs to a second OR'"'"'ing operation;

(i) using the results of the second OR'"'"'ing operation and the first ECC information as inputs to a third ECC correction operation; and

(j) if the third ECC correction operation is successful and if the number of errors corrected exceeds a threshold, writing the corrected data to the flash memory module and invalidating the entry.

21. The method as in claim 20, further including:

(k) repeating steps (a)-(j) for all entries in the metadata table that contain information designating the first portion of the flash memory module.

22. The method as in claim 21, further including:

(l) performing steps (a)-(k) for all entries in the metadata table that contain information designating a second portion of the flash memory module, the performance of the steps for the first portion overlapping the performance of the steps for the second portion.

23. The method as in claim 22, in which:

at least some performances of step (a) for the first portion are preceded by checking a first worklist associated with the first portion, with the performance of step (a) for the first portion being delayed if entries are present in the first worklist; and

at least some performances of step (a) for the second portion are preceded by checking a second worklist associated with the second portion, with the performance of step (a) for the second portion being delayed if entries are present in the first worklist;

whereby, the presence of entries on the first worklist does not affect performance of the method for the second portion and the presence of entries on the second worklist does not affect performance of the method for the first portion.

24. The method as in claim 23, further including:

(m) following performance of step (k) for all entries designating the first portion, waiting for a designated event, and then repeating the performance of step (k) for all entries designated the first portion; and

(n) following performance of step (l) for all entries designating the second portion, waiting for a designated event, and then repeating the performance of step (1) for all entries designated the second portion.

25. The method as in claim 25 in which:

the first portion consists of at least two flash dies, and the second portion consists of at least two flash dies, and the flash dies contained in the first portion are different than the flash dies contained in the second portion.