High-Speed Receiver Architecture

• US 20090185613A1
• Filed: 12/15/2008
• Published: 07/23/2009
• Est. Priority Date: 10/03/2005
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: ClariPhy Communications Incorporated (Inphi Corporation)
• Inventors: Grace, Carl, Hueda, Mario R., Carrer, Hugo S., Crivelli, Diego E., Luna, German C., Agazzi, Oscar E.
• Granted Patent: US 8,139,630 B2
• Time in Patent Office: Days
• US Class Current: 375/232
• CPC Class Codes: H03M 1/0626 by filtering
• CPC Class Codes: H03M 1/0692 using a diminished radix representation, e.g. radix 1.95
• CPC Class Codes: H03M 1/0695 using less than the maximum number of output states per stage or step, e.g. 1.5 per stage or less than 1.5 bit per stage type
• CPC Class Codes: H03M 1/1042 the look-up table containing corrected values for replacing the original digital values H03M1/1052 takes precedence
• CPC Class Codes: H03M 1/1215 using time-division multiplexing
• CPC Class Codes: H03M 1/181 in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values
• CPC Class Codes: H03M 1/42 Sequential comparisons in series-connected stages with no change in value of analogue signal
• CPC Class Codes: H03M 1/44 Sequential comparisons in series-connected stages with change in value of analogue signal
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 25/0204 of multiple channels
• CPC Class Codes: H04L 25/03038 with a non-recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 7/0004 Initialisation of the receiver H04L7/0075 and H04L7/10 take precedence
• CPC Class Codes: H04L 7/0062 detection of error based on data decision error, e.g. Mueller type detection
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection

Abstract

A receiver (e.g., for a 10 G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.

Claims

1. A receiver comprising:

an interleaved ADC having multiple ADC channels; and

a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels, the multi-channel equalizer comprising;

a feedforward equalizer (FFE) coupled to a Viterbi decoder having a channel estimator, the channel estimator based on a Volterra series model of the channel.

2. The receiver of claim 1 wherein the Volterra series model is a weighted sum of input bits, products of input bits, and a constant term.

3. The receiver of claim 2 wherein the Volterra series model is a weighted sum of a constant, N individual input bits, and all possible products containing two or more of those N input bits.