Imaging device

• US 20090190015A1
• Filed: 06/11/2008
• Published: 07/30/2009
• Est. Priority Date: 01/30/2008
• Status: Active Grant

• Current Assignee: HL Klemove Corporation
• Original Assignee: Gentex Corporation
• Inventors: Andrus, Jeremy C., Bechtel, Jon H.
• Granted Patent: US 8,587,706 B2
• Time in Patent Office: Days
• US Class Current: 348/302
• CPC Class Codes: H04N 23/741 by increasing the dynamic range of the image compared to the dynamic range of the electronic image sensors
• CPC Class Codes: H04N 25/53 Control of the integration time
• CPC Class Codes: H04N 25/531 by controlling rolling shutters in CMOS SSIS
• CPC Class Codes: H04N 25/533 by using differing integration times for different sensor regions
• CPC Class Codes: H04N 25/74 Circuitry for scanning or addressing the pixel array
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array

Abstract

The present invention relates to improved imaging devices having high dynamic range and to monitoring and automatic control systems incorporating the improved imaging devices.

Claims

1. An imaging device, comprising:

an array of pixels arranged in columns comprising signal means which serve to enable any given pixel within any given column; and

an integration period selection circuit associated with each column, wherein said integration period selection circuit is configured to receive a signal from an enabled pixel and initiate a selected integration period for said enabled pixel.

2. An imaging device as in claim 1 wherein a transistor in a pixel responds to concurrence of a signal which enables said pixel in said column and the signal to select the integration period for the enabled pixel.

3. An imaging device as in claim 2 wherein said transistor is a selective transfer gate operation logic function transistor and is connected to a transfer gate in said pixel.

4. An imaging device as in claim 3 wherein a selective transfer gate operation logic function transistor is located on a common substrate proximate each pixel within said array of pixels.

5. An imaging device as in claim 3 wherein said pixels are based on a 4T pixel structure.

6. An imaging device as in claim 2 wherein said transistor is a selective reset logic function transistor and is connected to a reset transistor in said pixel.

7. An imaging device as in claim 6 wherein a selective reset logic function transistor is located on a common substrate proximate each pixel within said array of pixels.

8. An imaging device as in claim 6 wherein said pixels are based on a 3T pixel structure.

9. An imaging device as in claim 1 wherein an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

10. An imaging device as in claim 1 wherein a start of an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

11. An imaging device, comprising:

an array of pixels, said pixels are based on a 4T pixel structure;

each of said pixels further comprising a selective transfer gate operation logic function transistor connected to a transfer gate.

12. An imaging device as in claim 11 said selective transfer gate operation logic function transistor responds to concurrence of a signal which enables said pixel and a signal to select an integration period for said pixel

13. An imaging device as in claim 11 wherein a selective transfer gate operation logic function transistor is located on a common substrate proximate each pixel within said array of pixels.

14. An imaging device as in claim 11 wherein an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

15. An imaging device as in claim 11 wherein a start of an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

16. Am imaging devices as in claim 11 configured to operate greater than 25 frames/second.

17. Am imaging devices as in claim 11 comprising greater than 130 dB dynamic range.

18. An imaging device, comprising:

an array of pixels, said pixels are based on a 3T pixel structure;

each of said pixels further comprising a selective reset logic function transistor connected to a reset transistor, wherein an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

19. An imaging device as in claim 18 said selective reset logic function transistor responds to concurrence of a signal which enables said pixel and a signal to select an integration period for said pixel

20. An imaging device as in claim 18 wherein a selective reset logic function transistor is located on a common substrate proximate each pixel within said array of pixels.

21. An imaging device as in claim 19 wherein an integration period for each pixel within said array of pixels is independently determined within a corresponding image acquisition sequence.

22. An imaging device as in claim 18 wherein a start of an integration period for each pixel within said array of pixels is dynamically determined within a corresponding image acquisition sequence.

23. Am imaging devices as in claim 18 configured to operate greater than 25 frames/second.

24. Am imaging devices as in claim 18 comprising greater than 130 dB dynamic range.

25. An imaging device, comprising:

columns of pixels, each column comprising a column circuit configured to receive an input from any selected pixel from an associated column, said column circuit is further configured to automatically select an integration period for a selected pixel and to output a signal to said selected pixel to initiate a selected integration period, wherein a first transistor within each pixel is configured to receive a first signal indicating when the pixel within said column is currently selected and a second signal from an associated column circuit indicating a selected integration period for said selected pixel, wherein said transistor outputs a signal which at least in part controls initiation of the selected integration period for said selected pixel.

26. An imaging device as in claim 25 wherein said first transistor is coupled to a transfer gate transistor which initiates transfer of charge from a light induced charge accumulating site within said selected pixel to a charge storage site within said selected pixel, this action being used at least in part to initiate a selectable integration period chosen for the pixel.

27. An imaging device as in claim 25 wherein said first transistor is coupled to a reset transistor which resets said selected pixel to perform tasks which include initiation of a selectable integration period for said selected pixel.

28. An imaging device as in claim 26 wherein pixel structure is based on a 4T pixel design.

29. An imaging device as in claim 27 wherein pixel structure is based on a 3T pixel design.

30. An imaging devices as in claim 25 configured to operate greater than 30 frames/second.

31. An imaging devices as in claim 25 comprising greater than 130 dB dynamic range.

32. An imaging device, comprising:

at least a substantial subset of columns of pixels, each said column of pixels in said subset comprising a column circuit configured to receive an input from a selected pixel from an associated column, said column circuit is further configured to automatically select an integration period for said selected pixel and to output a signal to said selected pixel to initiate a selected integration period.

33. An imaging device as in claim 32 wherein all columns comprise a column circuit.

34. An imaging device as in claim 32 wherein said input to said column circuit from said selected pixel is an analog input.

35. An imaging device as in claim 34 wherein said analog input is compared to an analog threshold value within said column circuit.

36. An imaging device as in claim 32, each said column circuit comprising a memory associated with said selected pixel to record an indication of said selected integration period for said selected pixel.

37. An imaging device as in claim 36 wherein settings in said memory are used at least in part, to select an integration period for said selected pixel.

38. An imaging device as in claim 35 wherein the result of said comparison is used in part to select an integration period for said selected pixel.

39. An imaging device as in claim 32 wherein said column circuit is configured to receive an input from a selected pixel in an associated column, to select an integration period for said selected pixel and to output a signal to said selected pixel to initiate said selected integration period within a single task.

40. An imaging device as in claim 32 wherein conditional selection and initiation of integration periods occurs substantially in parallel for multiple columns, each column comprising an associated column circuit.

41. An imaging device as in claim 32 wherein a first transistor within each pixel is configured to receive a first signal indicating when the pixel within said column is currently selected and a second signal from an associated column circuit indicating a selected integration period for said selected pixel, wherein said transistor outputs a signal which at least in part controls initiation of said selected integration period for said selected pixel.

42. An imaging device as in claim 41 wherein said first transistor is coupled to a transfer gate transistor which initiates transfer of charge from a light induced charge accumulating site within said selected pixel to a charge storage site within said selected pixel, this action being used at least in part to initiate a selectable integration period chosen for the pixel.

43. An imaging device as in claim 41 wherein said first transistor is coupled to a reset transistor which resets said selected pixel to-perform tasks which include initiation of a selectable integration period for said selected pixel.

44. An imaging device as in claim 32 each said pixel comprising an anti-blooming control circuit.

45. An imaging device as in claim 32 wherein pixel structure is based on a 3T pixel design.

46. An imaging device as in claim 32 wherein pixel structure is based on a 4T pixel design.

47. An imaging device as in claim 32 wherein digitized pixel readout is performed using at least one circuit at least partially distinct from a column circuit associated with selected column.

48. An imaging device as in claim 47 wherein pixel values are digitized during time periods that at least partially overlap time periods during which integration periods are chosen and initiated for pixels.

49. An imaging device as in claim 32 wherein pixel values are digitized only once per image acquisition sequence.

50. An imaging device as in claim 32 wherein selected integration periods are selected from a discrete set of available integration periods.

51. An imaging device as in claim 50 wherein available integration periods end at the same time.

52. An imaging device as in claim 32 wherein a value indicative of the light received by a pixel is based on the digitized pixel value and the integration period chosen for the pixel.

53. An imaging device as in claim 52 wherein values indicative of the light received by pixels is output in a conventional order as part of a rasterized scan sequence.

54. An imaging device as in claim 51 wherein integration periods available for pixels start at different times.

55. An imaging devices as in claim 32 configured to operate greater than 25 frames/second.

56. Am imaging devices as in claim 32 comprising greater than 130 dB dynamic range.