TRANSLATION TABLE COHERENCY MECAHANISM USING CACHE WAY AND SET INDEX WRITE BUFFERS

• US 20090193193A1
• Filed: 01/28/2008
• Published: 07/30/2009
• Est. Priority Date: 01/28/2008
• Status: Active Grant

• Current Assignee: Valley Device Management
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Kern, William
• Granted Patent: US 8,041,895 B2
• Time in Patent Office: Days
• US Class Current: 711/128
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems and/or methods are presented that provide for recording transactions that occur during a write process in an organized, self-aggregated manner for the purpose of recovering the transactions in the event of a power loss. By implementing an organization that reflects the cache architecture that is organized according to the cache way and set index of each transaction, the amount of time and effort required to recover the modified data from a sudden loss of power event is minimized. In this regard, the cache way and set index cache architecture provides for a post-power loss search operation that is limited to identifying duplicate locations within the cache-line and keeping only the most recent modification. By providing for such pre-organization in terms of self-aggregation by cache way and set index recording, the overall search process is greatly reduced and flexibility can be implemented in cache-line eviction processing in the event that the cache is determined to be full.

Claims

1. A memory system that insures data recovery in the event of a memory operation failure, comprising:

a non-volatile memory; and

an organization that reflects a cache architecture stored in the non-volatile memory and including a plurality of cache way and set index write buffers that are operable for storing one or more address-modifying transactions that occur during a memory write operation based on the cache being way and set associative.

2. The memory system of claim 1 further comprising a volatile memory in communication with the non-volatile memory and an address translation table stored in at least one of the volatile memory and the non-volatile memory, wherein the address translation table is operable for mapping a addresses from a first coordinate system to addresses in a second coordinate system during the memory write operation.

3. The memory system of claim 2, further comprising an inverse translation table stored in at least one of the volatile memory and the non-volatile memory, wherein the inverse translation table is operable for mapping the for mapping the second coordinate system addresses to the first coordinate system addresses.

4. The memory system of claim 1, wherein the cache includes a plurality of cache ways, each cache way including a plurality of associated set indexes.

5. The memory system of claim 1, wherein the cache includes four cache ways, each of the four cache ways including a plurality of associated set indexes.

6. The memory system of claim 1, wherein the plurality of cache way and set index write buffers each further include a write buffer table, wherein each write buffer table is associated with a corresponding cache way and set index.

7. The memory system of claim 6, wherein the write buffer table includes write transaction indexes indicating an index for each write transaction associated with the corresponding cache way and set index.

8. The memory system of claim 7, wherein each write transaction index has corresponding entries in the table for a first coordinate system address, a second coordinate system address, and a timestamp.

9. The memory system of claim 2, further comprising a recovery module stored in at least one of the volatile memory and the non-volatile memory and operable to identify locations where information has been recorded in non-volatile data store memory based on transaction information in the write buffers and, based on the transaction information, establish a last-in-time translation for the address.

10. The memory system of claim 9, wherein the recovery module is further operable to establish a last-in-time translation for an address based on the transaction information in the write buffers.

11. The memory system of claim 9, wherein the recovery module is further operable to store the last-in-time translation in non-volatile memory.

12. An electronic device comprising the system of claim 1.

13. The electronic device of claim 12, the electronic device is one of a computer, a cellular phone, a digital phone, a video device, a smart card, a personal digital assistant, a television, an electronic game, a digital camera, an electronic organizer, an audio player, an audio recorder, an electronic device associated with digital rights management, a Personal Computer Memory Card International Association (PCMCIA) card, a trusted platform module (TPM), an electronic control unit associated with a motor vehicle, a global positioning satellite (GPS) device, an electronic device associated with an airplane, an electronic device associated with an industrial control system, a Hardware Security Module (HSM), a set-top box, a secure memory device with computational capabilities, or an electronic device with at least one tamper-resistant chip.

14. A method for recording write operation transactions in a non-volatile memory system, comprising:

providing for a non-volatile memory including an organization that reflects a cache architecture having a plurality of write buffers that organize storage locations according to set associative cache way and set index;

identifying a set index for an address of a write transaction and a cache way within the cache;

determining one of the plurality of write buffers as a storage location for the write transaction based on the identified cache way and set index; and

recording the write transaction in the storage location.

15. The method of claim 14, wherein providing for a non-volatile memory including an organization that reflects the cache architecture having a plurality of write buffers providing for a non-volatile memory including an organization that reflects the cache architecture having a plurality of write buffers that organize storage locations according to one or more cache ways, each cache way including a plurality of set indexes.

16. The method of claim 15, wherein providing for a non-volatile memory including an organization that reflects the cache architecture having a plurality of write buffers further comprises providing for a non-volatile memory including an organization that reflects the cache architecture having a plurality of write buffers, each write buffer including a write buffer table associated with a cache way and set index.

17. The method of claim 16, wherein providing for a non-volatile memory including an organization that reflects the cache architecture having a plurality of write buffers, each write buffer including a write buffer table, further comprises providing for a non-volatile memory including an organization that reflects the cache architecture having a plurality of write buffers, each write buffer including a write buffer table associated with a cache way and set index, wherein each table includes write transaction indexes, each write transaction index includes a first coordinate system address, a second coordinate system address and a timestamp.

18. The method of claim 14, wherein identifying a set index for an address of a write transaction further comprises identifying a set index for a first coordinate system address of a write transaction.

19. The method of claim 14, wherein identifying a set index for an address of a write transaction further comprises identifying a set index for a second coordinate system of a write transaction.

20. The method of claim 15, wherein identifying a cache way within the cache further comprises identifying one of a plurality of cache ways within the cache.