RESISTANCE-CHANGE MEMORY

• US 20090201717A1
• Filed: 02/05/2009
• Published: 08/13/2009
• Est. Priority Date: 02/07/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MAEDA, Takashi, UEDA, Yoshihiro, TSUCHIDA, Kenji
• Granted Patent: US 7,952,916 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods

Abstract

A resistance-change memory includes first and second bit lines running in the same direction, a third bit line running parallel to the first and second bit lines, fourth and fifth bit lines running in the same direction, a sixth bit line running parallel to the fourth and fifth bit lines, a first memory element which has one and the other terminals connected to the first and third bit lines, and changes to one of first and second resistance states, a first reference element having one and the other terminals connected to the fourth and sixth bit lines, and set in the first resistance state, a second reference element having one and the other terminals connected to the fifth and sixth bit lines, and set in the second resistance state, and a sense amplifier having first and second input terminals connected to the first and fourth bit lines.

Claims

1. A resistance-change memory comprising:

a first bit line and a second bit line extending in the same direction;

a third bit line extending parallel to the first bit line and the second bit line;

a fourth bit line and a fifth bit line extending in the same direction;

a sixth bit line extending parallel to the fourth bit line and the fifth bit line;

a first memory element which comprises a first terminal connected to the first bit line and a second terminal connected to the third bit line, and is configured to change to either a first resistance state or a second resistance state;

a first reference element comprising a first terminal connected to the fourth bit line and a second terminal connected to the sixth bit line, the first reference element being set in the first resistance state;

a second reference element making a pair with the first reference element, comprising a first terminal connected to the fifth bit line and a second terminal connected to the sixth bit line, the second reference element being set in the second resistance state; and

a sense amplifier comprising a first input terminal connected to the first bit line and a second input terminal connected to the fourth bit line.

2. The memory of claim 1, wherein a read current is supplied in a first direction to set the first reference element in the first resistance state, and in a second direction to set the second reference element in the second resistance state, while reading out data from the first memory element.

3. The memory of claim 1, wherein

the first memory element, the first reference element, and the second reference element comprise magneto resistive effect elements,

the first memory element comprises a first pinned layer in which a magnetization direction is fixed, a first free layer in which a magnetization direction changes in accordance with a direction of a write current, and a first nonmagnetic layer disposed between the first pinned layer and the first free layer,

the first reference element comprises a second pinned layer in which a magnetization direction is fixed, a second free layer in which a magnetization direction changes in accordance with a direction of a write current, and a second nonmagnetic layer disposed between the second pinned layer and the second free layer, and

the second reference element comprises a third pinned layer in which a magnetization direction is fixed, a third free layer in which a magnetization direction changes in accordance with a direction of a write current, and a third nonmagnetic layer disposed between the third pinned layer and the third free layer.

4. The memory of claim 3, which further comprises:

a first transistor comprising a first current path comprising a first end connected to the first pinned layer;

a second transistor comprising a second current path comprising a first end connected to the second pinned layer;

a third transistor comprising a third current path comprising a first end connected to the third pinned layer;

a first current source connected to the first bit line;

a second current source connected to the fourth bit line; and

a ground terminal connected to a second end of the first current path and the third free layer, wherein

magnetization directions in the second pinned layer and the second free layer are set parallel to each other in the memory,

magnetization directions in the third pinned layer and the third free layer are set antiparallel to each other in the memory, and

a second end of the second current path and a second end of the third current path are connected via the sixth bit line.

5. The memory of claim 1, wherein the first bit line and the second bit line are on the same straight line.

6. The memory of claim 1, wherein

the first reference element comprises a plurality of first reference elements, and the plurality of first reference elements are connected in parallel by the fourth bit line and the sixth bit line,

the second reference element comprises a plurality of second reference elements, and the plurality of second reference elements are connected in parallel by the fifth bit line and the sixth bit line,

the plurality of first reference elements connected to the fourth bit line are set in the first resistance state, and

the plurality of second reference elements connected to the fifth bit line are set in the second resistance state.

7. The memory of claim 1, further comprising:

a second memory element which comprises a first terminal connected to the fourth bit line and a second terminal connected to the sixth bit line, and is configured to change to either the first resistance state or the second resistance state;

a third reference element comprising a first terminal connected to the first bit line and a second terminal connected to the third bit line, the third reference element being set in the first resistance state; and

a fourth reference element making a pair with the third reference element, comprising a first terminal connected to the second bit line and a second terminal connected to the third bit line, the fourth reference element being set in the second resistance state.

8. The memory of claim 1, further comprising a second memory element which comprises a first terminal connected to the second bit line and a second terminal connected to the third bit line, and is configured to change to either the first resistance state or the second resistance state.

9. The memory of claim 8, further comprising a first transistor comprising a first current path comprising a first end connected to the first bit line and a second end connected to the second bit line, wherein

the first transistor is turned off while reading out data from the first memory element, and is turned on while reading out data from the second memory element.

10. The memory of claim 9, further comprising a second transistor comprising a second current path comprising a first end connected to the fourth bit line and a second end connected to the fifth bit line, wherein

the second transistor is turned off if the first reference element and the second reference element are used to generate a reference potential while reading out data from either the first memory element or the second memory element.

11. The memory of claim 1 further comprising:

a seventh bit line and an eighth bit line extending in the same direction;

a ninth bit line extending parallel to the seventh bit line and the eighth bit line;

a third reference element comprising a first terminal connected to the seventh bit line and a second terminal connected to the ninth bit line, the third reference element being set in the first resistance state; and

a fourth reference element making a pair with the third reference element, comprising a first terminal connected to the eighth bit line and a second terminal connected to the ninth bit line, the fourth reference element being set in the second resistance state, wherein

the first reference element, the second reference element, the third reference element, and the fourth reference element are used to generate a reference potential while reading out data from the first memory element.

12. The memory of claim 11, further comprising:

a first transistor comprising a first current path comprising a first end connected to the first reference element and a second end connected to the sixth bit line;

a second transistor comprising a second current path comprising a first end connected to the second reference element and a second end connected to the sixth bit line;

a third transistor comprising a third current path comprising a first end connected to the third reference element and a second end connected to the ninth bit line;

a fourth transistor comprising a fourth current path comprising a first end connected to the fourth reference element and a second end connected to the ninth bit line;

a first word line connected to gates of the first transistor and the third transistor; and

a second word line connected to gates of the second transistor and the fourth transistor.

13. The memory of claim 11, wherein the fourth bit line and the seventh bit line are connected, and the fifth bit line and the eighth bit line are connected.

14. The memory of claim 1, further comprising:

a first source and sink circuit for writing data connected to a first end of either the first bit line or the second bit line; and

a second source and sink circuit for writing data connected to a first end of the third bit line.

15. The memory of claim 1, which further comprises:

a second memory element which comprises a first terminal connected to the second bit line and a second terminal connected to the third bit line, and is configured to change to either the first resistance state or the second resistance state;

a third reference element comprising a first terminal connected to the first bit line and a second terminal connected to the third bit line, the third reference element being set in the first resistance state;

a fourth reference element making a pair with the third reference element, comprising a first terminal connected to the second bit line and a second terminal connected to the third bit line, the fourth reference element being set in the second resistance state;

a first source and sink circuit for writing data connected to a first end of the first bit line;

a second source and sink circuit for writing data connected to a first end of the third bit line;

a third source and sink circuit for writing data connected to a second end of the third bit line; and

a fourth source and sink circuit for writing data connected to a first end of the second bit line, wherein

the first source and sink circuit and either the second source and sink circuit or the third source and sink circuit are used while writing data in either the first memory element or the third reference element, and

the fourth source and sink circuit and either the second source and sink circuit or the third source and sink circuit are used while writing data in either the second memory element or the fourth reference element.

16. The memory of claim 1, further comprising:

a second memory element which comprises a first terminal connected to the second bit line and a second terminal connected to the third bit line, and is configured to change to either the first resistance state or the second resistance state;

a third reference element comprising a first terminal connected to the first bit line and a second terminal connected to the third bit line, the third reference element being set in the first resistance state;

a fourth reference element making a pair with the third reference element, comprising a first terminal connected to the second bit line and a second terminal connected to the third bit line, the fourth reference element being set in the second resistance state;

a first source and sink circuit for writing data connected to a first end of the first bit line and a first end of the third bit line;

a second source and sink circuit for writing data connected to a first end of the second bit line and a second end of the third bit line;

a first transistor formed between the first source and sink circuit and a first end of the first bit line;

a second transistor formed between the first source and sink circuit and a first end of the third bit line;

a third transistor formed between the second source and sink circuit and a first end of the second bit line; and

a fourth transistor formed between the second source and sink circuit and a second end of the third bit line, wherein

the first source and sink circuit and the second source and sink circuit are used by turning on the first transistor and the fourth transistor while writing data in either the first memory element or the third reference element, and

the first source and sink circuit and the second source and sink circuit are used by turning on the second transistor and the third transistor while writing data in either the second memory element or the fourth reference element.

17. The memory of claim 1, which further comprises:

a second memory element which comprises a first terminal connected to the second bit line and a second terminal connected to the third bit line, and is configured to change to either the first resistance state or the second resistance state;

a third reference element comprising a first terminal connected to the first bit line and a second terminal connected to the third bit line, and set in the first resistance state;

a fourth reference element making a pair with the third reference element, comprising a first terminal connected to the second bit line and a second terminal connected to the third bit line, and set in the second resistance state;

a first source and sink circuit for writing data connected to a first end of the first bit line;

a second source and sink circuit for writing data connected to a first end of the third bit line; and

a transistor comprising a current path comprising a first end connected to a second end of the first bit line, and the second end connected to a first end of the second bit line, wherein

the first source and sink circuit and the second source and sink circuit are used by turning off the transistor while writing data in either the first memory element or the third reference element, and

the first source and sink circuit and the second source and sink circuit are used by turning on the transistor while writing data in either the second memory element or the fourth reference element.

18. The memory of claim 1, wherein the first reference element and the second reference element are next to each other in a direction parallel to the first bit line, the second bit line, and the third bit line.

19. The memory of claim 1, wherein the first memory element is placed between the first reference element and the second reference element.

20. The memory of claim 1, further comprising:

a seventh bit line and an eighth bit line extending in the same direction;

a ninth bit line extending parallel to the seventh bit line and the eighth bit line;

a third reference element comprising a first terminal connected to the seventh bit line and a second terminal connected to the ninth bit line, the third reference element being set in the second resistance state;

a fourth reference element making a pair with the third reference element, comprising a first terminal connected to the eighth bit line and a second terminal connected to the ninth bit line, the fourth reference element being set in the first resistance state;

a first transistor connected in series with the first reference element;

a second transistor connected in series with the second reference element;

a third transistor connected in series with the third reference element;

a fourth transistor connected in series with the fourth reference element;

a first word line connected to gates of the first transistor and the third transistor; and

a second word line connected to gates of the second transistor and the fourth transistor.