TRIPLE LATCH FLIP FLOP SYSTEM AND METHOD

• US 20090212815A1
• Filed: 02/24/2009
• Published: 08/27/2009
• Est. Priority Date: 06/30/2006
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Pitkethly, Scott, Masleid, Robert P.
• Granted Patent: US 7,872,492 B2
• Time in Patent Office: Days
• US Class Current: 326/27
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356191 with synchronous operation

Abstract

A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.

Claims

1. A triple latch flip-flop system comprising:

a pull up latch for driving a pull up node;

a pull down latch for driving a pull down node;

a primary latch for recording a state; and

an output derived from the outputs of said pull up latch, pull down latch and said primary latch.

2. A triple latch flip flop system of claim 1 wherein said pull up latch, pull down latch and primary latch comprise static logic gates.

3. A triple latch flip flop system of claim 2 wherein said pull up latch comprises a priority on set operation.

4. A triple latch flip flop system of claim 2 wherein said pull down latch comprises a priority on reset operation.

5. A triple latch flip flop system of claim 1 wherein said pull up latch, pull down latch and primary latch comprise dynamic gates.

6. A triple latch flip flop system of claim 5 wherein said pull down latch comprises a priority on reset operation.

7. A triple latch flip flop system of claim 5 wherein said pull up latch comprises a priority on set operation.

8. A triple latch flip-flop method comprising:

precharging a triple latch flip flop system;

evaluating data through said triple latch flip flop system;

blocking data in said triple latch flip flop system; and

returning said triple latch flip flop system to a pre-charge state.

9. A triple latch flip-flop method of claim 8 wherein said precharging includes shutting off output drivers and putting a primary latch into a retention mode.

10. A triple latch flip-flop method of claim 8 wherein said prechagring includes

forcing a pull-up latch into a set state and a pull-down latch into a reset state.

11. A triple latch flip-flop method of claim 8 wherein said precharging weakly drives an output.

12. A triple latch flip-flop method of claim 8 wherein said precharging includes holding a output state until a clock trigger.

13. A triple latch flip-flop method of claim 8 wherein said evaluating includes clocking said triple latch flip flop system.

14. A triple latch flip-flop method of claim 8 wherein said evaluating includes releasing a state hold on a pull-up latch and pull-down latch.

15. A triple latch flip-flop method of claim 8 wherein said evaluating includes resetting a pull up latch.

16. A triple latch flip-flop method of claim 8 wherein said evaluating includes setting a pull down latch.

17. A triple latch flip-flop method of claim 8 wherein said evaluating

comprise resetting a pull up latch and strongly driving an output node;

setting a primary latch; and

instructing a pull down latch to reset.

18. A triple latch flip-flop method of claim 8 further comprising

performing race margin correction.

19. A triple latch flip-flop system comprising:

a skew correcting component for correcting clock skew;

a pull up latch for driving a pull up node;

a pull down latch for driving a pull down node; and

a primary latch for recording a state.

20. A triple latch flip-flop system of claim 19 further comprising a race suppression component for suppressing transition racing.

21. A triple latch flip-flop system of claim 19 further comprising a noise immunity component for reducing noise.

22. A triple latch flip-flop system of claim 19 further comprising a setup constraint component for adjusting setup constraints.

23. A triple latch flip-flop system of claim 19 further comprising a drive enhancement component.

24. A triple latch flip-flop system of claim 19 further comprising a scan component for test.