DIGITAL SYNTHESIZER FOR LOW POWER LOCATION RECEIVERS

• US 20090219099A1
• Filed: 02/28/2008
• Published: 09/03/2009
• Est. Priority Date: 02/28/2008
• Status: Active Grant

• Current Assignee: Qualcomm technologies international, ltd. (Qualcomm, Inc.)
• Original Assignee: Doug Schucker, Jeff E. Koeller, Jeff Ogren, Noshir Dubash, Raja Tupelly
• Inventors: Koeller, Jeff E., Tupelly, Raja, Ogren, Jeff, Schucker, Doug, Dubash, Noshir
• Granted Patent: US 7,616,064 B2
• Time in Patent Office: Days
• US Class Current: 331/16
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

A high-frequency phase locked loop synthesizer having a selectable fractional-N divider and integer divider along with a phase frequency detector implemented as a CMOS logic block.

Claims

1. A radio frequency (RF) phase locked loop (PLL) synthesizer, comprising:

a variable oscillator (VCO) that generates a clock signal;

a fractional-N divider that has an fractional-N divider output coupled to a delta sigma modulator and in receipt of the clock signal;

an integer divider that has an integer divider output in receipt of the clock signal; and

a phase frequency detector (PFD) in receipt of either the fractional-N divider output or the integer divider output that is selected with a bypass signal, where the fractional-N divider, integer divider and PFD are formed in a CMOS logic block.

2. The RF PLL synthesizer of claim 1, where the CMOS logic block further includes control logic for generating the bypass signal.

3. The RF PLL synthesizer of claim 1, further comprising a multiplexer in the CMOS logic block that selects between the output of the fractional-N divider and the other output of the integer divider.

4. The RF PLL synthesizer of claim 3, where the selection of the integer divider results in the clock signal being turned off to the Fractional-N divider.

5. The RF PLL synthesizer of claim 1, wherein the clock signal has a frequency of approximately 1571 MHz.

6. The PLL synthesizer of claim 1, where the integer divider is an integer divider that divides by 96.

7. The RF PLL synthesizer of claim 1, further includes a digital loop filter that receives an output from the phase frequency detector, where the digital loop filter is part of the CMOS logic block.

8. The RF PLL synthesizer of claim 1, where the VCO operates at twice the frequency required by a mixer.

9. The RF PLL synthesizer of claim 8, where a flip-flop divides a signal from the VCO by an integer.

10. The RF PLL synthesizer of claim 9, where the integer is two.

11. The RF PLL synthesizer of claim 8, wherein a signal from the flip-flop is divided by two prior to receipt by the fractional-N divider.

12. The RF PLL synthesizer of claim 1, where the integer divider is a programmable integer divider.

13. A method for radio frequency (RF) phase looked loop (PLL) synthesizing, comprising:

generating a clock signal with a variable oscillator (VCO);

dividing the clock signal with a fractional-N divider that has an fractional-N divider output coupled to a delta sigma modulator and in receipt of the clock signal;

dividing the clock signal with an integer divider that has an integer divider output in receipt of the clock signal; and

selecting either the fractional-N divider output or the integer divider output with a bypass signal to be processed by a phase frequency detector (PFD), where the selecting occurs in a CMOS logic block.

14. The method for RF PLL synthesizing of claim 13, where the generating of the bypass signal occurs in the CMOS logic block.

15. The method for RF PLL synthesizing of claim 13, further comprising selecting with a multiplexer in the CMOS logic block between the output of the fractional-N divider and the other output of the integer divider.

16. The method for RF PLL synthesizing of claim 15, where selecting the integer divider further includes turning off the clock signal to the Fractional-N divider.

17. The method for RF PLL synthesizing of claim 13, wherein the clock signal has a frequency of approximately 1571 MHz.

18. The method for RF PLL synthesizing of claim 13, where the dividing by the integer divider is by 96.

19. The method for RF PLL synthesizing of claim 13 further includes, filtering with a digital loop filter that receives an output from the phase frequency detector, where the digital loop filter is part of the CMOS logic block.

20. The method for RF PLL synthesizing of claim 13includes, operating the VCO at a frequency two times the frequency required by a mixer.

21. The method for RF PLL synthesizing of claim 20 further includes, dividing a signal from the VCO by an integer with a flip-flop.

22. The method for RF PLL synthesizing of claim 21, where dividing by an integer is dividing by two.

23. The method for RF PLL synthesizing of claim 20, includes dividing a signal from the flip-flop by two prior to receipt by the fractional-N divider.

24. The method for RF PLL synthesizing of claim 13, programming the integer divider coupled to the reference frequency, where the integer divider is a programmable integer divider.